SNLS336J October   2010  – November 2014 DS90UH925Q-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  DC and AC Serial Control Bus Characteristics
    8. 6.8  Recommended Timing for Serial Control Bus
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Charateristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Speed Forward Channel Data Transfer
      2. 7.3.2  Low Speed Back Channel Data Transfer
      3. 7.3.3  Backward Compatible Mode
      4. 7.3.4  Common Mode Filter Pin (CMF)
      5. 7.3.5  Video Control Signal Filter
      6. 7.3.6  Power Down (PDB)
      7. 7.3.7  Remote Auto Power Down Mode
      8. 7.3.8  LVCMOS VDDIO Option
      9. 7.3.9  Input PCLK Loss Detect
      10. 7.3.10 Serial Link Fault Detect
      11. 7.3.11 Pixel Clock Edge Select (RFB)
      12. 7.3.12 Low Frequency Optimization (LFMODE)
      13. 7.3.13 Interrupt Pin — Functional Description and Usage (INTB)
      14. 7.3.14 EMI Reduction Features
        1. 7.3.14.1 Input SSC Tolerance (SSCT)
        2. 7.3.14.2 GPIO[3:0] and GPO_REG[8:4]
          1. 7.3.14.2.1 GPIO[3:0] Enable Sequence
          2. 7.3.14.2.2 GPO_REG[8:4] Enable Sequence
        3. 7.3.14.3 I2S Transmitting
          1. 7.3.14.3.1 Secondary I2S Channel
        4. 7.3.14.4 HDCP
        5. 7.3.14.5 Built In Self Test (BIST)
          1. 7.3.14.5.1 BIST Configuration and Status
            1. 7.3.14.5.1.1 Sample BIST Sequence
          2. 7.3.14.5.2 Forward Channel and Back Channel Error Checking
        6. 7.3.14.6 Internal Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Select (MODE_SEL)
      2. 7.4.2 HDCP Repeater
      3. 7.4.3 Repeater Configuration
      4. 7.4.4 Repeater Connections
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
    6. 7.6 Register Maps
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Up Requirements and PDB Pin
    2. 9.2 CML Interconnect Guidelines
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

  • AN-2198 Exploring the Internal Test Pattern Generation SNLA132
  • AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines SNLA008
  • SCAN18245T Non-Inverting Transceiver with TRI-STATE Outputs SNLA035
  • TI Interface Website www.ti.com/lvds
  • AN-1187 Leadless Leadframe Package (LLP) SNOA401
  • Semiconductor and IC Package Thermal Metrics SPRA953

11.2 Trademarks

All other trademarks are the property of their respective owners.

11.3 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.