JAJSH12B November 2014 – August 2019 DS90UH929-Q1
PRODUCTION DATA.
PIN | I/O, TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
HDMI TMDS INPUT | |||
IN_CLK-
IN_CLK+ |
49
50 |
I, TMDS | TMDS Clock Differential Input |
IN_D0-
IN_D0+ |
55
56 |
I, TMDS | TMDS Data Channel 0 Differential Input |
IN_D1-
IN_D1+ |
59
60 |
I, TMDS | TMDS Data Channel 1 Differential Input |
IN_D2-
IN_D2+ |
62
63 |
I, TMDS | TMDS Data Channel 2 Differential Input |
OTHER HDMI | |||
HPD | 42 | O, Open-Drain | Hot Plug Detect Output. Pull up to RX_5V with a 1-kΩ resistor |
RX_5V | 43 | I | HDMI 5-V Detect Input |
DDC_SDA | 44 | IO, Open-Drain | DDC Slave Serial Data
Pullup to RX_5V with a 47-kΩ resistor |
DDC_SCL | 45 | I, Open-Drain | DDC Slave Serial Clock
Pullup to RX_5V with a 47-kΩ resistor |
CEC | 1 | IO, Open-Drain | Consumer Electronic Control Channel Input/Output Interface.
Pullup with a 27-kΩ resistor to 3.3 V |
X1 | 39 | I, LVCMOS | Optional Oscillator Input: This pin is the optional reference clock for CEC. It must be connected to a 25 MHz 0.1% (1000ppm), 45-55% duty cycle clock source at CMOS-level 1.8 V. Leave it open if unused. |
FPD-LINK III SERIAL | |||
DOUT- | 26 | O | FPD-Link III Inverting Output
The output must be AC-coupled with a 0.1-µF capacitor for interfacing with 92x deserializers and 33-nF capacitor for 94x deserializers |
DOUT+ | 27 | O | FPD-Link III True Output
The output must be AC-coupled with a 0.1-µF capacitor for interfacing with 92x deserializers and 33-nF capacitor for 94x deserializers |
LFT | 20 | Analog | FPD-Link III Loop Filter
Connect to a 10-nF capacitor to GND |
CONTROL | |||
SDA | 14 | IO, Open-Drain | I2C Data Input / Output Interface
Open-drain. Must have an external pullup to resistor to 1.8 V or 3.3 V. See I2CSEL pin. DO NOT FLOAT. Recommended pullup: 4.7 kΩ. |
SCL | 15 | IO, Open-Drain | I2C Clock Input / Output Interface
Open-drain. Must have an external pullup resistor to 1.8 V or 3.3 V. See I2CSEL pin. DO NOT FLOAT. Recommended pullup: 4.7 kΩ. |
I2CSEL | 6 | I, LVCMOS | I2C Voltage Level Strap Option
Tie to VDDIO with a 10-kΩ resistor for 1.8-V I2C operation. Leave floating for 3.3-V I2C operation. This pin is read as an input at power up. |
IDx | 19 | Analog | I2C Serial Control Bus Device ID Address Select |
MODE_SEL0 | 18 | Analog | Mode Select 0. See Table 4. |
MODE_SEL1 | 32 | Analog | Mode Select 1. See Table 4. |
PDB | 31 | I, LVCMOS | Power-Down Mode Input Pin |
INTB | 13 | O, Open-Drain | Open Drain. Remote interrupt. Active LOW.
Pullup to VDDIO with a 4.7-kΩ resistor. |
REM_INTB | 40 | O, Open-Drain | Remote interrupt. Mirrors status of INTB_IN from the deserializer.
Note: External pullup to 1.8 V required. Recommended pullup: 4.7 kΩ. INTB = H, Normal Operation INTB = L, Interrupt Request |
BIDIRECTIONAL CONTROL CHANNEL (BCC) GPIO PINS | |||
GPIO0 | 4 | IO, LVCMOS | BCC GPIO0. Shared with SDIN |
GPIO1 | 5 | IO, LVCMOS | BCC GPIO1. Shared with SWC |
GPIO2 | 37 | IO, LVCMOS | BCC GPIO2. Shared with I2S_DC |
GPIO3 | 38 | IO, LVCMOS | BCC GPIO3. Shared with I2S_DD |
REGISTER-ONLY GPIO | |||
GPIO5_REG | 36 | IO, LVCMOS | General-Purpose Input/Output 5
Local register control only. Shared with I2S_DB |
GPIO6_REG | 35 | IO, LVCMOS | General-Purpose Input/Output 6
Local register control only. Shared with I2S_DA |
GPIO7_REG | 33 | IO, LVCMOS | General-Purpose Input/Output 7
Local register control only. Shared with I2S_WC |
GPIO8_REG | 34 | IO, LVCMOS | General-Purpose Input/Output 8
Local register control only. Shared with I2S_CLK |
SLAVE MODE LOCAL I2S CHANNEL PINS | |||
I2S_WC | 33 | I, LVCMOS | Slave Mode I2S Word Clock Input. Shared with GPIO7_REG |
I2S_CLK | 34 | I, LVCMOS | Slave Mode I2S Clock Input. Shared with GPIO8_REG |
I2S_DA | 35 | I, LVCMOS | Slave Mode I2S Data Input. Shared with GPIO6_REG |
I2S_DB | 36 | I, LVCMOS | Slave Mode I2S Data Input. Shared with GPIO5_REG |
I2S_DC | 37 | I, LVCMOS | Slave Mode I2S Data Input. Shared with GPIO2 |
I2S_DD | 38 | I, LVCMOS | Slave Mode I2S Data Input. Shared with GPIO3 |
AUXILIARY I2S CHANNEL PINS | |||
SWC | 5 | O, LVCMOS | Master Mode I2S Word Clock Output. Shared with GPIO1 |
SCLK | 6 | O, LVCMOS | Master Mode I2S Clock Output. Shared with I2CSEL. This pin is sampled following power-up as I2CSEL, then it will switch to SCLK operation as an output. |
SDIN | 4 | I, LVCMOS | Master Mode I2S Data Input. Shared with GPIO0 |
MCLK | 16 | IO, LVCMOS | Master Mode I2S System Clock Input/Output |
POWER AND GROUND | |||
VTERM | 57 | Power | Must be connected to 3.3-V or 1.8-V supply.
Connect to 3.3-V (±5%) Supply if incoming video is DC coupled OR Connect to 1.8-V (±5%) Supply if incoming video is AC coupled Refer to Figure 22 or Figure 21. |
VDD18 | 24
51 64 |
Power | 1.8-V (±5%) Analog supply. Refer to Figure 22 or Figure 21. |
VDDA11 | 9 | Power | 1.1-V (±5%) Analog supply. Refer to Figure 22 or Figure 21. |
VDDHA11 | 52
54 58 61 |
Power | 1.1-V (±5%) TMDS supply. Refer to Figure 22 or Figure 21. |
VDDHS11 | 21
28 |
Power | 1.1-V (±5%) supply. Refer to Figure 22 or Figure 21. |
VDDL11 | 7
41 |
Power | 1.1-V (±5%) Digital supply. Refer to Figure 22 or Figure 21. |
VDDP11 | 17 | Power | 1.1-V (±5%) PLL supply. Refer to Figure 22 or Figure 21. |
VDDS11 | 25 | Power | 1.1-V (±5%) Serializer supply. Refer to Figure 22 or Figure 21. |
VDDIO | 3
46 |
Power | 1.8-V (±5%) IO supply. Refer to Figure 22 or Figure 21. |
GND | Thermal Pad | GND | Ground. Connect to Ground plane with at least 9 vias. |
OTHER | |||
RES0
RES1 |
2
29 |
Reserved. Tie to GND. | |
RES2 | 30 | Reserved. Connect with 50Ω to GND. | |
NC0
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 |
8
10 11 12 22 23 47 48 53 |
No connect. Leave floating. Do not connect to VDD or GND. |