SNLS478B NOVEMBER   2014  – May 2020 DS90UH940-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  Timing Requirements for the Serial ControlBus
    8. 6.8  Switching Characteristics
    9. 6.9  Timing Diagrams and Test Circuits
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  FPD-Link III Port Register Access
      4. 7.3.4  Clock and Output Status
      5. 7.3.5  LVCMOS VDDIO Option
      6. 7.3.6  Power Down (PDB)
      7. 7.3.7  Interrupt Pin — Functional Description and Usage (INTB_IN)
      8. 7.3.8  General-Purpose I/O (GPIO)
        1. 7.3.8.1 GPIOx and D_GPIOx Pin Configuration
        2. 7.3.8.2 Back Channel Configuration
        3. 7.3.8.3 GPIO_REG[8:5] Configuration
      9. 7.3.9  SPI Communication
        1. 7.3.9.1 SPI Mode Configuration
        2. 7.3.9.2 Forward Channel SPI Operation
        3. 7.3.9.3 Reverse Channel SPI Operation
      10. 7.3.10 Backward Compatibility
      11. 7.3.11 Adaptive Equalizer
        1. 7.3.11.1 Transmission Distance
        2. 7.3.11.2 Adaptive Equalizer Algorithm
        3. 7.3.11.3 AEQ Settings
          1. 7.3.11.3.1 AEQ Start-Up and Initialization
          2. 7.3.11.3.2 AEQ Range
          3. 7.3.11.3.3 AEQ Timing
      12. 7.3.12 I2S Audio Interface
        1. 7.3.12.1 I2S Transport Modes
        2. 7.3.12.2 I2S Jitter Cleaning
        3. 7.3.12.3 MCLK
      13. 7.3.13 HDCP
        1. 7.3.13.1 HDCP I2S Audio Encryption
      14. 7.3.14 Built-In Self Test (BIST)
        1. 7.3.14.1 BIST Configuration and Status
          1. 7.3.14.1.1 Sample BIST Sequence
        2. 7.3.14.2 Forward Channel and Back Channel Error Checking
      15. 7.3.15 Internal Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Select
        1. 7.4.1.1 1-Lane FPD-Link III Input, 4 MIPI® Lanes Output
        2. 7.4.1.2 1-Lane FPD-Link III Input, 2 MIPI® Lanes Output
        3. 7.4.1.3 2-Lane FPD-Link III Input, 4 MIPI® Lanes Output
        4. 7.4.1.4 2-Lane FPD-Link III Input, 2 MIPI® Lanes Output
        5. 7.4.1.5 1- or 2-Lane FPD-Link III Input, 2 or 4 MIPI® Lanes Output in Replicate
      2. 7.4.2 MODE_SEL[1:0]
      3. 7.4.3 CSI-2 Interface
      4. 7.4.4 Input Display Timing
      5. 7.4.5 MIPI® CSI-2 Output Data Formats
      6. 7.4.6 Non-Continuous / Continuous Clock
      7. 7.4.7 Ultra-Low-Power State (ULPS)
      8. 7.4.8 CSI-2 Data Identifier
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
      2. 7.5.2 Multi-Master Arbitration Support
      3. 7.5.3 I2C Restrictions on Multi-Master Operation
      4. 7.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
      5. 7.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
      6. 7.5.6 Restrictions on Control Channel Direction for Multi-Master Operation
    6. 7.6 Register Maps
      1. 7.6.1 DS90UH940-Q1 Registers
        1. 7.6.1.1  I2C_Device_ID Register (Address = 0h) [reset = Strap]
          1. Table 12. I2C_Device_ID Register Field Descriptions
        2. 7.6.1.2  Reset Register (Address = 1h) [reset = 4h]
          1. Table 13. Reset Register Field Descriptions
        3. 7.6.1.3  General_Configuration_0 Register (Address = 2h) [reset = 0h]
          1. Table 14. General_Configuration_0 Register Field Descriptions
        4. 7.6.1.4  General_Configuration_1 Register (Address = 3h) [reset = F0h]
          1. Table 15. General_Configuration_1 Register Field Descriptions
        5. 7.6.1.5  BCC_Watchdog_Control Register (Address = 4h) [reset = FEh]
          1. Table 16. BCC_Watchdog_Control Register Field Descriptions
        6. 7.6.1.6  I2C_Control_1 Register (Address = 5h) [reset = 1Eh]
          1. Table 17. I2C_Control_1 Register Field Descriptions
        7. 7.6.1.7  I2C_Control_2 Register (Address = 6h) [reset = 0h]
          1. Table 18. I2C_Control_2 Register Field Descriptions
        8. 7.6.1.8  REMOTE_ID Register (Address = 7h) [reset = 0h]
          1. Table 19. REMOTE_ID Register Field Descriptions
        9. 7.6.1.9  SlaveID_0 Register (Address = 8h) [reset = 0h]
          1. Table 20. SlaveID_0 Register Field Descriptions
        10. 7.6.1.10 SlaveID_1 Register (Address = 9h) [reset = 0h]
          1. Table 21. SlaveID_1 Register Field Descriptions
        11. 7.6.1.11 SlaveID_2 Register (Address = Ah) [reset = 0h]
          1. Table 22. SlaveID_2 Register Field Descriptions
        12. 7.6.1.12 SlaveID_3 Register (Address = Bh) [reset = 0h]
          1. Table 23. SlaveID_3 Register Field Descriptions
        13. 7.6.1.13 SlaveID_4 Register (Address = Ch) [reset = 0h]
          1. Table 24. SlaveID_4 Register Field Descriptions
        14. 7.6.1.14 SlaveID_5 Register (Address = Dh) [reset = 0h]
          1. Table 25. SlaveID_5 Register Field Descriptions
        15. 7.6.1.15 SlaveID_6 Register (Address = Eh) [reset = 0h]
          1. Table 26. SlaveID_6 Register Field Descriptions
        16. 7.6.1.16 SlaveID_7 Register (Address = Fh) [reset = 0h]
          1. Table 27. SlaveID_7 Register Field Descriptions
        17. 7.6.1.17 SlaveAlias_0 Register (Address = 10h) [reset = 0h]
          1. Table 28. SlaveAlias_0 Register Field Descriptions
        18. 7.6.1.18 SlaveAlias_1 Register (Address = 11h) [reset = 0h]
          1. Table 29. SlaveAlias_1 Register Field Descriptions
        19. 7.6.1.19 SlaveAlias_2 Register (Address = 12h) [reset = 0h]
          1. Table 30. SlaveAlias_2 Register Field Descriptions
        20. 7.6.1.20 SlaveAlias_3 Register (Address = 13h) [reset = 0h]
          1. Table 31. SlaveAlias_3 Register Field Descriptions
        21. 7.6.1.21 SlaveAlias_4 Register (Address = 14h) [reset = 0h]
          1. Table 32. SlaveAlias_4 Register Field Descriptions
        22. 7.6.1.22 SlaveAlias_5 Register (Address = 15h) [reset = 0h]
          1. Table 33. SlaveAlias_5 Register Field Descriptions
        23. 7.6.1.23 SlaveAlias_6 Register (Address = 16h) [reset = 0h]
          1. Table 34. SlaveAlias_6 Register Field Descriptions
        24. 7.6.1.24 SlaveAlias_7 Register (Address = 17h) [reset = 0h]
          1. Table 35. SlaveAlias_7 Register Field Descriptions
        25. 7.6.1.25 MAILBOX_18 Register (Address = 18h) [reset = 0h]
          1. Table 36. MAILBOX_18 Register Field Descriptions
        26. 7.6.1.26 MAILBOX_19 Register (Address = 19h) [reset = 1h]
          1. Table 37. MAILBOX_19 Register Field Descriptions
        27. 7.6.1.27 GPIO_9__Global_GPIO_Config Register (Address = 1Ah) [reset = 0h]
          1. Table 38. GPIO_9__Global_GPIO_Config Register Field Descriptions
        28. 7.6.1.28 Frequency_Counter Register (Address = 1Bh) [reset = 0h]
          1. Table 39. Frequency_Counter Register Field Descriptions
        29. 7.6.1.29 General_Status Register (Address = 1Ch) [reset = 0h]
          1. Table 40. General_Status Register Field Descriptions
        30. 7.6.1.30 GPIO0_Config Register (Address = 1Dh) [reset = 0h]
          1. Table 41. GPIO0_Config Register Field Descriptions
        31. 7.6.1.31 GPIO1_2_Config Register (Address = 1Eh) [reset = 0h]
          1. Table 42. GPIO1_2_Config Register Field Descriptions
        32. 7.6.1.32 GPIO_3_Config Register (Address = 1Fh) [reset = 0h]
          1. Table 43. GPIO_3_Config Register Field Descriptions
        33. 7.6.1.33 GPIO_5_6_Config Register (Address = 20h) [reset = 0h]
          1. Table 44. GPIO_5_6_Config Register Field Descriptions
        34. 7.6.1.34 GPIO_7_8_Config Register (Address = 21h) [reset = 0h]
          1. Table 45. GPIO_7_8_Config Register Field Descriptions
        35. 7.6.1.35 Datapath_Control Register (Address = 22h) [reset = 0h]
          1. Table 46. Datapath_Control Register Field Descriptions
        36. 7.6.1.36 RX_Mode_Status Register (Address = 23h) [reset = Strap]
          1. Table 47. RX_Mode_Status Register Field Descriptions
        37. 7.6.1.37 BIST_Control Register (Address = 24h) [reset = 8h]
          1. Table 48. BIST_Control Register Field Descriptions
        38. 7.6.1.38 BIST_ERROR_COUNT Register (Address = 25h) [reset = 0h]
          1. Table 49. BIST_ERROR_COUNT Register Field Descriptions
        39. 7.6.1.39 SCL_High_Time Register (Address = 26h) [reset = 83h]
          1. Table 50. SCL_High_Time Register Field Descriptions
        40. 7.6.1.40 SCL_Low_Time Register (Address = 27h) [reset = 84h]
          1. Table 51. SCL_Low_Time Register Field Descriptions
        41. 7.6.1.41 Datapath_Control_2 Register (Address = 28h) [reset = Loaded from SER]
          1. Table 52. Datapath_Control_2 Register Field Descriptions
        42. 7.6.1.42 I2S_Control Register (Address = 2Bh) [reset = 0h]
          1. Table 53. I2S_Control Register Field Descriptions
        43. 7.6.1.43 PCLK_Test_Mode Register (Address = 2Eh) [reset = 0h]
          1. Table 54. PCLK_Test_Mode Register Field Descriptions
        44. 7.6.1.44 DUAL_RX_CTL Register (Address = 34h) [reset = 1h]
          1. Table 55. DUAL_RX_CTL Register Field Descriptions
        45. 7.6.1.45 AEQ_CTL1 Register (Address = 35h) [reset = 0h]
          1. Table 56. AEQ_CTL1 Register Field Descriptions
        46. 7.6.1.46 MODE_SEL Register (Address = 37h) [reset = 0h]
          1. Table 57. MODE_SEL Register Field Descriptions
        47. 7.6.1.47 I2S_DIVSEL Register (Address = 3Ah) [reset = 0h]
          1. Table 58. I2S_DIVSEL Register Field Descriptions
        48. 7.6.1.48 Adaptive_EQ_Status Register (Address = 3Bh) [reset = 0h]
          1. Table 59. Adaptive_EQ_Status Register Field Descriptions
        49. 7.6.1.49 LINK_ERROR_COUNT Register (Address = 41h) [reset = 3h]
          1. Table 60. LINK_ERROR_COUNT Register Field Descriptions
        50. 7.6.1.50 HSCC_CONTROL Register (Address = 43h) [reset = 0h]
          1. Table 61. HSCC_CONTROL Register Field Descriptions
        51. 7.6.1.51 ADAPTIVE_EQ_BYPASS Register (Address = 44h) [reset = 60h]
          1. Table 62. ADAPTIVE_EQ_BYPASS Register Field Descriptions
        52. 7.6.1.52 AEQ_CTL2 Register (Address = 45h) [reset = 88h]
          1. Table 63. AEQ_CTL2 Register Field Descriptions
        53. 7.6.1.53 CML_OUTPUT_CTL1 Register (Address = 52h) [reset = 0h]
          1. Table 64. CML_OUTPUT_CTL1 Register Field Descriptions
        54. 7.6.1.54 CML_OUTPUT_ENABLE Register (Address = 56h) [reset = 0h]
          1. Table 65. CML_OUTPUT_ENABLE Register Field Descriptions
        55. 7.6.1.55 CML_OUTPUT_CTL2 Register (Address = 57h) [reset = 0h]
          1. Table 66. CML_OUTPUT_CTL2 Field Descriptions
        56. 7.6.1.56 CML_OUTPUT_CTL3 Register (Address = 63h) [reset = 0h]
          1. Table 67. CML_OUTPUT_CTL3 Field Descriptions
        57. 7.6.1.57 PGCTL Register (Address = 64h) [reset = 10h]
          1. Table 68. PGCTL Register Field Descriptions
        58. 7.6.1.58 PGCFG Register (Address = 65h) [reset = 0h]
          1. Table 69. PGCFG Register Field Descriptions
        59. 7.6.1.59 PGIA Register (Address = 66h) [reset = 0h]
          1. Table 70. PGIA Register Field Descriptions
        60. 7.6.1.60 PGID Register (Address = 67h) [reset = 0h]
          1. Table 71. PGID Register Field Descriptions
        61. 7.6.1.61 PGDBG Register (Address = 68h) [reset = 0h]
          1. Table 72. PGDBG Register Field Descriptions
        62. 7.6.1.62 PGTSTDAT Register (Address = 69h) [reset = 0h]
          1. Table 73. PGTSTDAT Register Field Descriptions
        63. 7.6.1.63 CSICFG0 Register (Address = 6Ah) [reset = 0h]
          1. Table 74. CSICFG0 Register Field Descriptions
        64. 7.6.1.64 CSICFG1 Register (Address = 6Bh) [reset = 0h]
          1. Table 75. CSICFG1 Register Field Descriptions
        65. 7.6.1.65 CSIIA Register (Address = 6Ch) [reset = 0h]
          1. Table 76. CSIIA Register Field Descriptions
        66. 7.6.1.66 CSIID Register (Address = 6Dh) [reset = 0h]
          1. Table 77. CSIID Register Field Descriptions
        67. 7.6.1.67 GPIO_Pin_Status_1 Register (Address = 6Eh) [reset = 0h]
          1. Table 78. GPIO_Pin_Status_1 Register Field Descriptions
        68. 7.6.1.68 GPIO_Pin_Status_2 Register (Address = 6Fh) [reset = 0h]
          1. Table 79. GPIO_Pin_Status_2 Register Field Descriptions
        69. 7.6.1.69 RX_BKSV0 Register (Address = 80h) [reset = 0h]
          1. Table 80. RX_BKSV0 Register Field Descriptions
        70. 7.6.1.70 RX_BKSV1 Register (Address = 81h) [reset = 0h]
          1. Table 81. RX_BKSV1 Register Field Descriptions
        71. 7.6.1.71 RX_BKSV2 Register (Address = 82h) [reset = 0h]
          1. Table 82. RX_BKSV2 Register Field Descriptions
        72. 7.6.1.72 RX_BKSV3 Register (Address = 83h) [reset = 0h]
          1. Table 83. RX_BKSV3 Register Field Descriptions
        73. 7.6.1.73 RX_BKSV4 Register (Address = 84h) [reset = 0h]
          1. Table 84. RX_BKSV4 Register Field Descriptions
        74. 7.6.1.74 TX_KSV0 Register (Address = 90h) [reset = 0h]
          1. Table 85. TX_KSV0 Register Field Descriptions
        75. 7.6.1.75 TX_KSV1 Register (Address = 91h) [reset = 0h]
          1. Table 86. TX_KSV1 Register Field Descriptions
        76. 7.6.1.76 TX_KSV2 Register (Address = 92h) [reset = 0h]
          1. Table 87. TX_KSV2 Register Field Descriptions
        77. 7.6.1.77 TX_KSV3 Register (Address = 93h) [reset = 0h]
          1. Table 88. TX_KSV3 Register Field Descriptions
        78. 7.6.1.78 TX_KSV4 Register (Address = 94h) [reset = 0h]
          1. Table 89. TX_KSV4 Register Field Descriptions
        79. 7.6.1.79 HDCP_DBG Register (Address = C0h) [reset = 0h]
          1. Table 90. HDCP_DBG Register Field Descriptions
        80. 7.6.1.80 HDCP_DBG2 Register (Address = C1h) [reset = 0h]
          1. Table 91. HDCP_DBG2 Register Field Descriptions
        81. 7.6.1.81 HDCP_STS Register (Address = C4h) [reset = 0h]
          1. Table 92. HDCP_STS Register Field Descriptions
        82. 7.6.1.82 KSV_FIFO_DATA Register (Address = C9h) [reset = 0h]
          1. Table 93. KSV_FIFO_DATA Register Field Descriptions
        83. 7.6.1.83 KSV_FIFO_ADDR0 Register (Address = CAh) [reset = 0h]
          1. Table 94. KSV_FIFO_ADDR0 Register Field Descriptions
        84. 7.6.1.84 KSV_FIFO_ADDR1 Register (Address = CBh) [reset = 0h]
          1. Table 95. KSV_FIFO_ADDR1 Register Field Descriptions
        85. 7.6.1.85 RPTR_TX0 Register (Address = E0h) [reset = 0h]
          1. Table 96. RPTR_TX0 Register Field Descriptions
        86. 7.6.1.86 RPTR_TX1 Register (Address = E1h) [reset = 0h]
          1. Table 97. RPTR_TX1 Register Field Descriptions
        87. 7.6.1.87 RPTR_TX2 Register (Address = E2h) [reset = 0h]
          1. Table 98. RPTR_TX2 Register Field Descriptions
        88. 7.6.1.88 RPTR_TX3 Register (Address = E3h) [reset = 0h]
          1. Table 99. RPTR_TX3 Register Field Descriptions
        89. 7.6.1.89 HDCP_RX_ID0 Register (Address = F0h) [reset = 5Fh]
          1. Table 100. HDCP_RX_ID0 Register Field Descriptions
        90. 7.6.1.90 HDCP_RX_ID1 Register (Address = F1h) [reset = 55h]
          1. Table 101. HDCP_RX_ID1 Register Field Descriptions
        91. 7.6.1.91 HDCP_RX_ID2 Register (Address = F2h) [reset = 48h]
          1. Table 102. HDCP_RX_ID2 Register Field Descriptions
        92. 7.6.1.92 HDCP_RX_ID3 Register (Address = F3h) [reset = 39h]
          1. Table 103. HDCP_RX_ID3 Register Field Descriptions
        93. 7.6.1.93 HDCP_RX_ID4 Register (Address = F4h) [reset = 34h]
          1. Table 104. HDCP_RX_ID4 Register Field Descriptions
        94. 7.6.1.94 HDCP_RX_ID5 Register (Address = F5h) [reset = 30h]
          1. Table 105. HDCP_RX_ID5 Register Field Descriptions
      2. 7.6.2 CSI-2 Indirect Registers
        1. 7.6.2.1 CSI_TCK_TRAIL Register (Address = 2h) [reset = 0h]
          1. Table 107. CSI_TCK_TRAIL Register Field Descriptions
        2. 7.6.2.2 RAW_ALIGN Register (Address = 9h) [reset = 0h]
          1. Table 108. RAW_ALIGN Register Field Descriptions
        3. 7.6.2.3 CSI_EN_PORT0 Register (Address = 13h) [reset = 3Fh]
          1. Table 109. CSI_EN_PORT0 Register Field Descriptions
        4. 7.6.2.4 CSI_EN_PORT1 Register (Address = 14h) [reset = 0h]
          1. Table 110. CSI_EN_PORT1 Register Field Descriptions
        5. 7.6.2.5 CSIPASS Register (Address = 16h) [reset = 2h]
          1. Table 111. CSIPASS Register Field Descriptions
        6. 7.6.2.6 CSI_VC_ID Register (Address = 2Eh) [reset = 0h]
          1. Table 112. CSI_VC_ID Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 FPD-Link III Interconnect Guidelines
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
    2. 9.2 Power Sequence
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Ground
    3. 10.3 Routing FPD-Link III Signal Traces
    4. 10.4 CSI-2 Guidelines
    5. 10.5 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.8 Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT
HSTX DRIVER
HSTXDBR Data bit rate MIPI 2 lanes CSI0_D0±
CSI0_D1±
CSI0_D2±
CSI0_D3±
CSI1_D0±
CSI1_D1±
CSI1_D2±
CSI1_D3±
CSI0_CLK±
CSI1_CLK±		 350 1344 Mbps
MIPI 4 lanes 175 1190
fCLK DDR Clock frequency MIPI 2 lanes 175 672 MHz
MIPI 4 lanes 87.5 595
ΔVCMTX(HF) Common mode voltage variations HF Above 450 MHz 15 mVRMS
ΔVCMTX(LF) Common mode voltage variations LF Between 50 and 450 MHz 25 mVRMS
tRHS
tFHS 		20% to 80% rise and fall HS HS bit rates ≤ 1 Gbps (UI ≥ 1 ns) 0.3 UI
HS bit rates > 1 Gbps (UI < 1 ns) 0.35 UI
Applicable for all HS bit rates. However, to avoid excessive radiation, bit rates ≤ 1 Gbps (UI ≥ 1 ns), must not use values below 150 ps. 100 ps
SDDTX TX differential return loss fLPMAX –18 dB
fH -9 dB
fMAX –3 dB
LPTX DRIVER
tRLP Rise time LP(2) 15% to 85% rise time CSI0_D0±
CSI0_D1±
CSI0_D2±
CSI0_D3±
CSI1_D0±
CSI1_D1±
CSI1_D2±
CSI1_D3±
CSI0_CLK±
CSI1_CLK±		 25 ns
tFLP Fall time LP(2) 15% to 85% fall time 25 ns
tREOT Rise time post-EoT(2) 30% to 85% rise time 35 ns
tLP-PULSE-TX Pulse width of the LP exclusive-OR clock(2) First LP exclusive-OR clock pulse after stop state or last pulse before stop state 40 ns
All other pulses 20 ns
tLP-PER-TX Period of the LP exclusive-OR clock 90 ns
DV/DtSR Slew rate(2) CLOAD = 0 pF 500 mV/ns
CLOAD = 5 pF 300 mV/ns
CLOAD = 20 pF 250 mV/ns
CLOAD = 70 pF 150 mV/ns
CLOAD = 0 to 70 pF (falling edge only) 30 mV/ns
CLOAD = 0 to 70 pF (rising edge only) 30 mV/ns
CLOAD = 0 to 70 pF (rising edge only) 30 – 0.075 × (VO,INST – 700) mV/ns
CLOAD Load capacitance(2) 0 70 pF
DATA-CLOCK TIMING SPECIFICATIONS (Figure 10)
UIINST UI instantaneous fCLK = CSI-2 DDR clock frequency CSI0_D0±
CSI0_D1±
CSI0_D2±
CSI0_D3±
CSI1_D0±
CSI1_D1±
CSI1_D2±
CSI1_D3±
CSI0_CLK±
CSI1_CLK±		 1/(fCLK × 2) UI
ΔUI UI variation
PCLK = 25 - 96MHz		 UI ≥ 1 ns –10% 10% UI
UI < 1 ns –5% 5% UI
tSKEW(TX) Data to clock skew (measured at transmitter)
Skew between clock and data from ideal center		 Data rate ≤ 1 Gbps –0.15 0.15 UIINST
Data rate > 1 Gbps –0.2 0.2 UIINST
CSI-2 TIMING SPECIFICATIONS (Figure 11, Figure 12)
tCLK-MISS Timeout for receiver to detect absence of clock transitions and disable the clock lane HS-RX CSI0_D0±
CSI0_D1±
CSI0_D2±
CSI0_D3±
CSI1_D0±
CSI1_D1±
CSI1_D2±
CSI1_D3±
CSI0_CLK±
CSI1_CLK±		 60 ns
tCLK-POST HS exit 60 + 52 × UI ns
tCLK-PRE Time HS clock shall be driver prior to any associated data lane beginning the transition from LP to HS mode 8 UI
tCLK-PREPARE Clock lane HS Entry 38 95 ns
tCLK-SETTLE Time interval during which the HS receiver shall ignore any clock lane HS transitions 95 300 ns
tCLK-TERM-EN Timeout at clock lane display module to enable HS Termination Time for Dn to reach VTERM-EN 38 ns
tCLK-TRAIL Time that the transmitter drives the HS-0 state after the last payload clock bit of a HS transmission burst 60 ns
tCLK-PREPARE + tCLK-ZERO TCLK-PREPARE + time that the transmitter drives the HS-0 state prior to starting the Clock 300 ns
tD-TERM-EN Time for the Data Lane receiver to enable the HS line termination Time for Dn to reach V-TERM-EN 35 + 4 × UI ns
tEOT Transmitted time interval from the start of tHS-TRAIL to the start of the LP-11 state following a HS burst see(1) 105 + 12 × UI ns
tHS-EXIT Time that the transmitter drives LP=11 following a HS burst 100 ns
tHS-PREPARE Data lane HS entry 40 + 4 × UI 85 + 6 × UI ns
tHS-PREPARE + tHS-ZERO tHS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the sync sequence 145 + 10 × UI ns
tHS-SETTLE Time interval during which the HS receiver ignores any data lane HS transitions, starting from the beginning of tHS-SETTLE 85 + 6 × UI 145 + 10 × UI ns
tHS-SKIP Time interval during which the HS-RX should ignore any transitions on the data lane, following a HS burst. The end point of the interval is defined as the beginning of the LP-11 state following the HS burst. 40 55 + 4 × UI ns
tHS-TRAIL Data lane HS exit 60 + 4 × UI ns
tLPX Transmitted length of LP state 50 ns
tWAKEUP Recovery time from ultra-low-power state (ULPS) 1 ms
(1) a. 1280 × 720p60; PCLK = 74.25 MHz; 4 MIPI lanes reg0x6c=0x02;reg0x6d=0x84
b. 1280 × 720p60; PCLK = 74.25MHz; 2 MIPI lanes reg0x6c=0x02; reg0x6d=0x89
c. 640 × 480p60; PCLK = 25 MHz; 4 MIPI lanes reg0x6c=0x02; reg0x6d=0x82
d. 640 × 480p60; PCLK = 25 MHz; 2 MIPI lanes reg0x6c=0x02; reg0x6d=0x83
e. Other video formats may require additional register configuration.
(2) CLOAD includes the low-frequencyequivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be<10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2-nsdelay.