JAJSG03 August   2018 DS90UH949A-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  DC Electrical Characteristics
    6. 7.6  AC Electrical Characteristics
    7. 7.7  DC and AC Serial Control Bus Characteristics
    8. 7.8  Recommended Timing for the Serial Control Bus
    9. 7.9  Timing Diagrams
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High-Definition Multimedia Interface (HDMI)
        1. 8.3.1.1 HDMI Receive Controller
      2. 8.3.2  Transition Minimized Differential Signaling
      3. 8.3.3  Enhanced Display Data Channel
      4. 8.3.4  Extended Display Identification Data (EDID)
        1. 8.3.4.1 External Local EDID (EEPROM)
        2. 8.3.4.2 Internal EDID (SRAM)
        3. 8.3.4.3 External Remote EDID
        4. 8.3.4.4 Internal Pre-Programmed EDID
      5. 8.3.5  Consumer Electronics Control (CEC)
      6. 8.3.6  +5-V Power Signal
      7. 8.3.7  Hot Plug Detect (HPD)
      8. 8.3.8  High-Speed Forward Channel Data Transfer
      9. 8.3.9  Back Channel Data Transfer
      10. 8.3.10 FPD-Link III Port Register Access
      11. 8.3.11 Power Down (PDB)
      12. 8.3.12 Serial Link Fault Detect
      13. 8.3.13 Interrupt Pin (INTB)
      14. 8.3.14 Remote Interrupt Pin (REM_INTB)
      15. 8.3.15 General-Purpose I/O
        1. 8.3.15.1 GPIO[3:0] and D_GPIO[3:0] Configuration
        2. 8.3.15.2 Back Channel Configuration
        3. 8.3.15.3 GPIO_REG[8:5] Configuration
      16. 8.3.16 SPI Communication
        1. 8.3.16.1 SPI Mode Configuration
        2. 8.3.16.2 Forward Channel SPI Operation
        3. 8.3.16.3 Reverse Channel SPI Operation
      17. 8.3.17 Backward Compatibility
      18. 8.3.18 Audio Modes
        1. 8.3.18.1 HDMI Audio
        2. 8.3.18.2 DVI I2S Audio Interface
          1. 8.3.18.2.1 I2S Transport Modes
          2. 8.3.18.2.2 I2S Repeater
        3. 8.3.18.3 AUX Audio Channel
        4. 8.3.18.4 TDM Audio Interface
      19. 8.3.19 HDCP
        1. 8.3.19.1 HDCP I2S Audio Encryption
      20. 8.3.20 Built-In Self Test (BIST)
        1. 8.3.20.1 BIST Configuration and Status
        2. 8.3.20.2 Forward Channel and Back Channel Error Checking
      21. 8.3.21 Internal Pattern Generation
        1. 8.3.21.1 Pattern Options
        2. 8.3.21.2 Color Modes
        3. 8.3.21.3 Video Timing Modes
        4. 8.3.21.4 External Timing
        5. 8.3.21.5 Pattern Inversion
        6. 8.3.21.6 Auto Scrolling
        7. 8.3.21.7 Additional Features
      22. 8.3.22 Spread Spectrum Clock Tolerance
    4. 8.4 Device Functional Modes
      1. 8.4.1 Mode Select Configuration Settings (MODE_SEL[1:0])
      2. 8.4.2 FPD-Link III Modes of Operation
        1. 8.4.2.1 Single Link Operation
        2. 8.4.2.2 Dual Link Operation
        3. 8.4.2.3 Replicate Mode
        4. 8.4.2.4 Auto-Detection of FPD-Link III Modes
        5. 8.4.2.5 Frequency detection circuit may reset the FPD-Link III PLL during a temperature ramp
    5. 8.5 Programming
      1. 8.5.1 Serial Control Bus
      2. 8.5.2 Multi-Master Arbitration Support
      3. 8.5.3 I2C Restrictions on Multi-Master Operation
      4. 8.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
      5. 8.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
      6. 8.5.6 Restrictions on Control Channel Direction for Multi-Master Operation
      7. 8.5.7 Prevention of I2C Faults During Abrupt System Faults
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Applications Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 High-Speed Interconnect Guidelines
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT
GPIO FREQUENCY(4)
Rb,FC Forward channel GPIO frequency Single-lane, IN_CLK = 25 MHz – 105 MHz GPIO[3:0], D_GPIO[3:0] 0.25 × IN_CLK MHz
Dual-lane, IN_CLK/2 = 25 MHz – 105 MHz 0.125 × IN_CLK
tGPIO,FC GPIO pulse width, forward channel Single-lane, IN_CLK = 25 MHz – 105 MHz GPIO[3:0], D_GPIO[3:0] >2 / IN_CLK s
Dual-lane, IN_CLK/2 = 25 MHz – 105 MHz >2 / (IN_CLK/2)
TMDS INPUT
Skew-Intra Maximum intra-pair skew IN_CLK±, IN_D[2:0]± 0.4 UITMDS(1)
Skew-Inter Maximum inter-pair skew 0.2 × Tchar(2) + 1.78 ns
ITJIT Input total jitter tolerance Per HDMI CTS ver 1.4b(5)
Per Test ID 8-7: TMDS - Jitter Tolerance
IN_CLK± 0.3 UITMDS(1)
FPD-LINK III OUTPUT
tLHT Low voltage differential low-to-high transition time 80 ps
tHLT Low voltage differential high-to-low transition time 80 ps
tXZD Output active to OFF delay PDB = L 100 ns
tPLD Lock time (HDMI Rx) 12 ms
tSD Delay — latency IN_CLK± 145 × T(1) s
tDJIT Output total jitter (see Figure 5) Random Pattern Single-lane: measured with CDR loop BW = f/15 (7MHz) 0.3 UIFPD3(3)
Dual-lane: measured with CDR loop BW = f/30 (7MHz)
λSTXBW Jitter transfer function
(-3-dB bandwidth)		 960 kHz
δSTX Jitter transfer function peaking 0.1 dB
(1) One bit period of the TMDS input.
(2) Ten bit periods of the TMDS input.
(3) One bit period of the serializer output.
(4) Back channel rates are available on the companion deserializer datasheet.
(5) Per Test ID 8-7: TMDS - Jitter Tolerance:
1) D_JITTER = 500kHz, C_JITTER = 10MHz
    Set C_JITTER component to 0.25*TBIT at TP1
    Set D_JITTER component to 0.3*TBIT at TP1
2) Set C_JITTER component to 0.25*TBIT at TP1
    Set D_JITTER component to 0.3TBIT at TP1D_JITTER = 1MHz, C_JITTER = 7MHz
    Set C_JITTER component to 0.25*TBIT at TP1
    Set D_JITTER component to 0.3*TBIT at TP1

Note: TP1 is the edges of eye diagram shown in the HDMI specification
A CDR filter is applied at 4MHz with BER ≤1 E-10