JAJSG03 August   2018 DS90UH949A-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  DC Electrical Characteristics
    6. 7.6  AC Electrical Characteristics
    7. 7.7  DC and AC Serial Control Bus Characteristics
    8. 7.8  Recommended Timing for the Serial Control Bus
    9. 7.9  Timing Diagrams
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High-Definition Multimedia Interface (HDMI)
        1. 8.3.1.1 HDMI Receive Controller
      2. 8.3.2  Transition Minimized Differential Signaling
      3. 8.3.3  Enhanced Display Data Channel
      4. 8.3.4  Extended Display Identification Data (EDID)
        1. 8.3.4.1 External Local EDID (EEPROM)
        2. 8.3.4.2 Internal EDID (SRAM)
        3. 8.3.4.3 External Remote EDID
        4. 8.3.4.4 Internal Pre-Programmed EDID
      5. 8.3.5  Consumer Electronics Control (CEC)
      6. 8.3.6  +5-V Power Signal
      7. 8.3.7  Hot Plug Detect (HPD)
      8. 8.3.8  High-Speed Forward Channel Data Transfer
      9. 8.3.9  Back Channel Data Transfer
      10. 8.3.10 FPD-Link III Port Register Access
      11. 8.3.11 Power Down (PDB)
      12. 8.3.12 Serial Link Fault Detect
      13. 8.3.13 Interrupt Pin (INTB)
      14. 8.3.14 Remote Interrupt Pin (REM_INTB)
      15. 8.3.15 General-Purpose I/O
        1. 8.3.15.1 GPIO[3:0] and D_GPIO[3:0] Configuration
        2. 8.3.15.2 Back Channel Configuration
        3. 8.3.15.3 GPIO_REG[8:5] Configuration
      16. 8.3.16 SPI Communication
        1. 8.3.16.1 SPI Mode Configuration
        2. 8.3.16.2 Forward Channel SPI Operation
        3. 8.3.16.3 Reverse Channel SPI Operation
      17. 8.3.17 Backward Compatibility
      18. 8.3.18 Audio Modes
        1. 8.3.18.1 HDMI Audio
        2. 8.3.18.2 DVI I2S Audio Interface
          1. 8.3.18.2.1 I2S Transport Modes
          2. 8.3.18.2.2 I2S Repeater
        3. 8.3.18.3 AUX Audio Channel
        4. 8.3.18.4 TDM Audio Interface
      19. 8.3.19 HDCP
        1. 8.3.19.1 HDCP I2S Audio Encryption
      20. 8.3.20 Built-In Self Test (BIST)
        1. 8.3.20.1 BIST Configuration and Status
        2. 8.3.20.2 Forward Channel and Back Channel Error Checking
      21. 8.3.21 Internal Pattern Generation
        1. 8.3.21.1 Pattern Options
        2. 8.3.21.2 Color Modes
        3. 8.3.21.3 Video Timing Modes
        4. 8.3.21.4 External Timing
        5. 8.3.21.5 Pattern Inversion
        6. 8.3.21.6 Auto Scrolling
        7. 8.3.21.7 Additional Features
      22. 8.3.22 Spread Spectrum Clock Tolerance
    4. 8.4 Device Functional Modes
      1. 8.4.1 Mode Select Configuration Settings (MODE_SEL[1:0])
      2. 8.4.2 FPD-Link III Modes of Operation
        1. 8.4.2.1 Single Link Operation
        2. 8.4.2.2 Dual Link Operation
        3. 8.4.2.3 Replicate Mode
        4. 8.4.2.4 Auto-Detection of FPD-Link III Modes
        5. 8.4.2.5 Frequency detection circuit may reset the FPD-Link III PLL during a temperature ramp
    5. 8.5 Programming
      1. 8.5.1 Serial Control Bus
      2. 8.5.2 Multi-Master Arbitration Support
      3. 8.5.3 I2C Restrictions on Multi-Master Operation
      4. 8.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
      5. 8.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
      6. 8.5.6 Restrictions on Control Channel Direction for Multi-Master Operation
      7. 8.5.7 Prevention of I2C Faults During Abrupt System Faults
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Applications Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 High-Speed Interconnect Guidelines
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.16 SPI Communication

The SPI Control Channel uses the secondary link in a 2-lane FPD-Link III implementation. Two possible modes are available: Forward Channel and Reverse Channel modes. In Forward Channel mode, the SPI Master is located at the Serializer, such that the direction of sending SPI data is in the same direction as the video data. In Reverse Channel mode, the SPI Master is located at the Deserializer, such that the direction of sending SPI data is in the opposite direction as the video data.

The SPI Control Channel can operate in a high-speed mode when writing data, but must operate at lower frequencies when reading data. During SPI reads, data is clocked from the slave to the master on the SPI clock falling edge. Thus, the SPI read must operate with a clock period that is greater than the round-trip data latency. On the other hand, data for SPI writes can be sent at much higher frequencies where the MISO pin can be ignored by the master.

SPI data rates are not symmetrical for the two modes of operation. Data over the forward channel can be sent much faster than data over the reverse channel.

NOTE

SPI cannot be used to access Serializer / Deserializer registers.