SNLS231P September   2006  – August 2024 DS90UR124-Q1 , DS90UR241-Q1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Serializer Input Timing Requirements for TCLK
    7. 5.7 Serializer Switching Characteristics
    8. 5.8 Deserializer Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Initialization and Locking Mechanism
      2. 6.3.2  Data Transfer
      3. 6.3.3  Resynchronization
      4. 6.3.4  Powerdown
      5. 6.3.5  Tri-State
      6. 6.3.6  Pre-Emphasis
      7. 6.3.7  AC-Coupling and Termination
        1. 6.3.7.1 Receiver Termination Option 1
        2. 6.3.7.2 Receiver Termination Option 2
        3. 6.3.7.3 Receiver Termination Option 3
      8. 6.3.8  Signal Quality Enhancers
      9. 6.3.9  @SPEED-BIST Test Feature
      10. 6.3.10 Backward-Compatible Mode With DS90C241 and DS90C124
    4. 6.4 Device Functional Modes
  8.   Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Using the DS90UR241 and DS90UR124
      2. 7.1.2 Display Application
      3. 7.1.3 Typical Application Connection
    2. 7.2 Typical Applications
      1. 7.2.1 DS90UR241-Q1 Typical Application Connection
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Power Considerations
          2. 7.2.1.2.2 Noise Margin
          3. 7.2.1.2.3 Transmission Media
          4. 7.2.1.2.4 46
          5. 7.2.1.2.5 Live Link Insertion
        3. 7.2.1.3 Application Curves
      2. 7.2.2 DS90UR124 Typical Application Connection
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 PCB Layout and Power System Considerations
        2. 7.4.1.2 LVDS Interconnect Guidelines
      2. 7.4.2 Layout Examples
  9. 7Device and Documentation Support
    1. 7.1 Device Support
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation
    3. 7.3 Receiving Notification of Documentation Updates
    4. 7.4 Support Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Glossary
  10. 8Revision History
  11.   Mechanical, Packaging, and Orderable Information

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AC-Coupling and Termination

The DS90UR241 and DS90UR124 supports AC-coupled interconnects through integrated DC balanced encoding/decoding scheme. To use the Serializer and Deserializer in an AC-coupled application, insert external AC-coupling capacitors in series in the LVDS signal path as illustrated in Figure 7-8. The Deserializer input stage is designed for AC-coupling by providing a built-in AC bias network which sets the internal VCM to +1.8V. With AC signal coupling, capacitors provide the AC-coupling path to the signal input.

For the high-speed LVDS transmissions, the smallest available package must be used for the AC-coupling capacitor. This helps minimize degradation of signal quality due to package parasitics. The most common used capacitor value for the interface is a 100nF (0.1uF). NPO class 1 or X7R class 2 type capacitors are recommended. 50 WVDC must be the minimum used for the best system-level ESD performance.

A termination resistor across DOUT± and RIN± is also required for proper operation to be obtained. The termination resistor must be equal to the differential impedance of the media being driven and in the range of 90 to 132Ω. 100Ω is a typical value common used with standard 100Ω transmission media. This resistor is required for control of reflections and also completes the current loop. Place the resistor as close to the Serializer DOUT± outputs and Deserializer RIN± inputs to minimize the stub length from the pins. To match with the deferential impedance on the transmission line, the LVDS I/O are terminated with 100Ω resistors on Serializer DOUT± outputs pins and Deserializer RIN± input pins.