JAJSPA3A November   2022  – December 2022 ESD1LIN24

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—JEDEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
  7. 7 Typical Characteristics – ESD1LIN24
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 IO Capacitance
      2. 8.3.2 IEC 61000-4-5 Surge Protection
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DYF|2
サーマルパッド・メカニカル・データ
発注情報

6.6 Electrical Characteristics

over TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage –24 24 V
VBRF Breakdown voltage(1) IIO = 10 mA 25.5 35.5 V
VBRR IIO = –10 mA –35.5 –25.5
VCLAMP Clamping voltage(2) IPP = 4.3 A, tp = 8/20 µs, from IO to GND 37 42 V
Clamping voltage(3) IPP = 16 A, TLP, from IO to GND 40
ILEAK Leakage current, any IO pin to GND VIO = ±24 V -50 1 50 nA
RDYN Dynamic resistance(3) 0.5 Ω
CL Line capacitance, any IO to GND VIO = 0 V, f = 1 MHz, Vp-p = 30 mV 2.3 3.8 pF
(1) VBRF and VBRR are defined as the voltage when ±10 mA is applied in the positive-going direction, before the device latches into the snapback state.
(2) Device stressed with 8/20 μs exponential decay waveform according to IEC 61000-4-5.
(3) Non-repetitive current pulse, Transmission Line Pulse (TLP); square pulse; ANSI / ESD STM5.5.1-2008