JAJSK18C April   2022  – November 2022 ESD2CAN24-Q1 , ESD2CANFD24-Q1 , ESD2CANXL24-Q1

PRODMIX  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 ESD Ratings - ISO Specification
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Thermal Information
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics – ESD2CAN24-Q1
    9. 6.9 Typical Characteristics – ESD2CANFD24-Q1
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 AEC-Q101 Qualified and Temperature Range
      2. 7.3.2 ISO 10605 ESD Protection
      3. 7.3.3 IEC 61000-4-5 Surge Protection
      4. 7.3.4 IO Capacitance
      5. 7.3.5 Dynamic Resistance
      6. 7.3.6 DC Breakdown Voltage
      7. 7.3.7 Ultra Low Leakage Current
      8. 7.3.8 Clamping Voltage
      9. 7.3.9 Industry Standard Leaded Packages
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4 Device Functional Modes

The ESD2CANxx24-Q1 is a dual channel passive clamp that has low leakage during normal operation when the voltage between pin 1 or pin 2 and pin 3 is below VRWM, and activates when the voltage between pin 1 or pin 2 and pin 3 goes above VBR. During ISO 10605 ESD events, transient voltages as high as ±30 kV can be clamped on either channel. When the voltages on the protected lines fall below the VHOLD, the device reverts back to the low leakage passive state.