JAJST80 February   2024 ESD652-Q1

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings - AEC Specifications
    3. 5.3 ESD Ratings - IEC Specifications
    4. 5.4 ESD Ratings - ISO Specifications
    5. 5.5 Recommended Operating Conditions
    6. 5.6 Thermal Information
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6Application and Implementation
    1. 6.1 Application Information
  8. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 ドキュメントの更新通知を受け取る方法
    3. 7.3 サポート・リソース
    4. 7.4 Trademarks
    5. 7.5 静電気放電に関する注意事項
    6. 7.6 用語集
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DBZ|3
サーマルパッド・メカニカル・データ
発注情報

5.7 Electrical Characteristics

At TA = 25°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage IIO < 50nA -18 18 V
ILEAK Leakage current at VRWM VIO = ±18V, I/O to GND 1 50 nA
VBR Breakdown voltage, I/O to GND (1) IIO = ±10mA 19 25 V
VCLAMP Surge clamping voltage, tp = 8/20 µs (2) IPP = ±1A, I/O to GND 22 25 V
IPP = ±5.5A, I/O to GND 25 32 V
VCLAMP TLP clamping voltage,  tp = 100 ns  (3) IPP = ±16A TLP, I/O to GND 28 V
RDYN Dynamic resistance (4) I/O to GND 0.32 Ω
GND to I/O 0.32
CLINE Line capacitance, IO to GND VIO = 0V, f = 1MHz 4 pF
(1) VBR is defined as the voltage obtained at 10mA when sweeping the voltage up, before the device latches into the snapback state
(2) Device stressed with 8/20µs exponential decay waveform according to IEC 61000-4-5
(3) Non-repetitive square wave current pulse, Transmission Line Pulse (TLP);  ANSI / ESD STM5.5.1-2008
(4) Extraction of RDYN using least squares fit of TLP characteristics between I = 10A and I = 20A