JAJSSD7A December   2023  – February 2024 ESDS552

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings - JEDEC Specifications
    3. 5.3 ESD Ratings - IEC Specifications
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. 6Application and Implementation
    1. 6.1 Application Information
  8. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 ドキュメントの更新通知を受け取る方法
    3. 7.3 サポート・リソース
    4. 7.4 Trademarks
    5. 7.5 静電気放電に関する注意事項
    6. 7.6 用語集
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DBZ|3
サーマルパッド・メカニカル・データ
発注情報

5.6 Electrical Characteristics

At TA = 25°C unless otherwise noted
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VRWMReverse stand-off voltageIIO < 50nA-1212V
ILEAKAGELeakage current at VRWMVIO = ±12V1050nA
VBR

Breakdown voltage, IO to GND and GND to IO(1)

IIO = ±1mA13.2

18

V
VCLAMPSurge clamping voltage, tp = 8/20µs(2)IPP = 1A, I/O to GND19V
IPP = 1A, GND to I/O19V

IPP = 20A, I/O to GND

23.5V
IPP = 20A, GND to I/O23.5V

RDYN

8/20µs surge Dynamic Resistance

I/O to GND

0.4Ω

GND to I/O

0.38

CLine

Line capacitance, IO to GND

VIO = 0V, f = 1MHz

9.511pF
(1) VBR is defined as the voltage obtained at 1mA when sweeping the voltage up, before the device latches into the snapback state
(1) Device stressed with 8/20µs exponential decay waveform according to IEC61000-4-5