JAJSJA4L June   2011  – February 2021 F28M35E20B , F28M35H22C , F28M35H52C , F28M35H52C-Q1 , F28M35M22C , F28M35M52C

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1. 3.1 機能ブロック図
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
      1. 6.2.1 Signal Descriptions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Automotive
    3. 7.3  ESD Ratings – Commercial
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK
      2. 7.5.2 Current Consumption at 100-MHz C28x SYSCLKOUT and 100-MHz M3SSCLK
      3. 7.5.3 Current Consumption at 75-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK
      4. 7.5.4 Current Consumption at 60-MHz C28x SYSCLKOUT and 60-MHz M3SSCLK
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics for RFP PowerPAD Package
    8. 7.8  Thermal Design Considerations
    9. 7.9  Timing and Switching Characteristics
      1. 7.9.1 Power Sequencing
        1. 7.9.1.1 Reset ( XRS) Timing Requirements
        2. 7.9.1.2 Reset ( XRS) Switching Characteristics
        3. 7.9.1.3 Power Management and Supervisory Circuit Solutions
      2. 7.9.2 Clock Specifications
        1. 7.9.2.1 Changing the Frequency of the Main PLL
        2. 7.9.2.2 Input Clock Frequency and Timing Requirements, PLL Lock Times
          1. 7.9.2.2.1 Input Clock Frequency
          2. 7.9.2.2.2 Crystal Oscillator Electrical Characteristics
          3. 7.9.2.2.3 X1 Timing Requirements - PLL Enabled (1)
          4. 7.9.2.2.4 X1 Timing Requirements - PLL Disabled
          5. 7.9.2.2.5 XCLKIN Timing Requirements - PLL Enabled
          6. 7.9.2.2.6 XCLKIN Timing Requirements - PLL Disabled
          7. 7.9.2.2.7 PLL Lock Times
        3. 7.9.2.3 Output Clock Frequency and Switching Characteristics
          1. 7.9.2.3.1 Output Clock Frequency
          2. 7.9.2.3.2 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (1)
        4. 7.9.2.4 Internal Clock Frequencies
          1. 7.9.2.4.1 Internal Clock Frequencies (150-MHz Devices)
      3. 7.9.3 Timing Parameter Symbology
        1. 7.9.3.1 General Notes on Timing Parameters
        2. 7.9.3.2 Test Load Circuit
      4. 7.9.4 Flash Timing – Master Subsystem
        1. 7.9.4.1 Master Subsystem – Flash/OTP Endurance
        2. 7.9.4.2 Master Subsystem – Flash Parameters
        3. 7.9.4.3 Master Subsystem – Flash/OTP Access Timing
        4. 7.9.4.4 Master Subsystem – Flash Data Retention Duration
        5. 7.9.4.5 Master Subsystem – Minimum Required Flash/OTP Wait States at Different Frequencies
      5. 7.9.5 Flash Timing – Control Subsystem
        1. 7.9.5.1 Control Subsystem – Flash/OTP Endurance
        2. 7.9.5.2 Control Subsystem – Flash Parameters
        3. 7.9.5.3 Control Subsystem – Flash/OTP Access Timing
        4. 7.9.5.4 Control Subsystem – Flash Data Retention Duration
      6. 7.9.6 GPIO Electrical Data and Timing
        1. 7.9.6.1 GPIO - Output Timing
          1. 7.9.6.1.1 General-Purpose Output Switching Characteristics
        2. 7.9.6.2 GPIO - Input Timing
          1. 7.9.6.2.1 General-Purpose Input Timing Requirements
        3. 7.9.6.3 Sampling Window Width for Input Signals
        4. 7.9.6.4 Low-Power Mode Wakeup Timing
          1. 7.9.6.4.1 IDLE Mode Timing Requirements
          2. 7.9.6.4.2 IDLE Mode Switching Characteristics
          3. 7.9.6.4.3 IDLE Entry and Exit Timing Diagram
          4. 7.9.6.4.4 STANDBY Mode Timing Requirements
          5. 7.9.6.4.5 STANDBY Mode Switching Characteristics
          6. 7.9.6.4.6 STANDBY Entry and Exit Timing Diagram
          7. 7.9.6.4.7 HALT Mode Timing Requirements
          8. 7.9.6.4.8 HALT Mode Switching Characteristics
          9. 7.9.6.4.9 HALT Entry and Exit Timing Diagram
      7. 7.9.7 External Interrupt Electrical Data and Timing
        1. 7.9.7.1 External Interrupt Timing Requirements
        2. 7.9.7.2 External Interrupt Switching Characteristics
        3. 7.9.7.3 External Interrupt Timing Diagram
    10. 7.10 Analog and Shared Peripherals
      1. 7.10.1 Analog-to-Digital Converter
        1. 7.10.1.1 Sample Mode
        2. 7.10.1.2 Start-of-Conversion Triggers
        3. 7.10.1.3 Analog Inputs
        4. 7.10.1.4 ADC Result Registers and EOC Interrupts
        5. 7.10.1.5 ADC Electrical Data and Timing
          1. 7.10.1.5.1 ADC Electrical Characteristics
          2. 7.10.1.5.2 External ADC Start-of-Conversion Switching Characteristics
          3. 7.10.1.5.3 ADCSOCAO or ADCSOCBO Timing Diagram
      2. 7.10.2 Comparator + DAC Units
        1. 7.10.2.1 On-Chip Comparator and DAC Electrical Data and Timing
          1. 7.10.2.1.1 Electrical Characteristics of the Comparator/DAC
      3. 7.10.3 Interprocessor Communications
      4. 7.10.4 External Peripheral Interface
        1. 7.10.4.1 EPI General-Purpose Mode
        2. 7.10.4.2 EPI SDRAM Mode
        3. 7.10.4.3 EPI Host Bus Mode
          1. 7.10.4.3.1 EPI 8-Bit Host Bus (HB-8) Mode
            1. 7.10.4.3.1.1 HB-8 Muxed Address/Data Mode
            2. 7.10.4.3.1.2 HB-8 Non-Muxed Address/Data Mode
            3. 7.10.4.3.1.3 HB-8 FIFO Mode
          2. 7.10.4.3.2 EPI 16-Bit Host Bus (HB-16) Mode
            1. 7.10.4.3.2.1 HB-16 Muxed Address/Data Mode
            2. 7.10.4.3.2.2 HB-16 Non-Muxed Address/Data Mode
            3. 7.10.4.3.2.3 HB-16 FIFO Mode
        4. 7.10.4.4 EPI Electrical Data and Timing
          1. 7.10.4.4.1 EPI SDRAM Interface Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (see Figure 1-1 , Figure 1-1 , and Figure 1-1 )
          2. 7.10.4.4.2 EPI SDRAM Timing Diagrams
          3. 7.10.4.4.3 EPI Host-Bus 8 and Host-Bus 16 Interface Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (see Figure 1-1 , Figure 1-1 , Figure 1-1 , and Figure 1-1 )
          4. 7.10.4.4.4 EPI Host-Bus 8 and Host-Bus 16 Interface Timing Requirements (1) (see Figure 1-1 and Figure 1-1 )
          5. 7.10.4.4.5 EPI Host-Bus 8/16 Mode Timing Diagrams
          6. 7.10.4.4.6 EPI General-Purpose Interface Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (see Figure 1-1 )
          7. 7.10.4.4.7 EPI General-Purpose Interface Timing Requirements (see Figure 1-1 and Figure 1-1 )
          8. 7.10.4.4.8 EPI General-Purpose Interface Timing Diagrams
    11. 7.11 Master Subsystem Peripherals
      1. 7.11.1 Synchronous Serial Interface
        1. 7.11.1.1 Bit Rate Generation
        2. 7.11.1.2 Transmit FIFO
        3. 7.11.1.3 Receive FIFO
        4. 7.11.1.4 Interrupts
        5. 7.11.1.5 Frame Formats
      2. 7.11.2 Universal Asynchronous Receiver/Transmitter
        1. 7.11.2.1 Baud-Rate Generation
        2. 7.11.2.2 Transmit and Receive Logic
        3. 7.11.2.3 Data Transmission and Reception
        4. 7.11.2.4 Interrupts
      3. 7.11.3 Cortex-M3 Inter-Integrated Circuit
        1. 7.11.3.1 Functional Overview
        2. 7.11.3.2 Available Speed Modes
        3. 7.11.3.3 I2C Electrical Data and Timing
          1. 7.11.3.3.1 I2C Timing
      4. 7.11.4 Cortex-M3 Controller Area Network
        1. 7.11.4.1 Functional Overview
      5. 7.11.5 Cortex-M3 Universal Serial Bus Controller
        1. 7.11.5.1 Functional Description
      6. 7.11.6 Cortex-M3 Ethernet Media Access Controller
        1. 7.11.6.1 Functional Overview
        2. 7.11.6.2 MII Signals
        3. 7.11.6.3 EMAC Electrical Data and Timing
          1. 7.11.6.3.1 Timing Requirements for MIITXCK (see Figure 1-1 )
          2. 7.11.6.3.2 MIITXCK Timing Diagrams
          3. 7.11.6.3.3 Timing Requirements for MIIRXCK (see Figure 1-1 )
          4. 7.11.6.3.4 MIIRXCK Timing Diagram
          5. 7.11.6.3.5 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for EMAC MII Transmit (see Figure 1-1 )
          6. 7.11.6.3.6 EMAC MII Transmit Timing Diagram
          7. 7.11.6.3.7 Timing Requirements for EMAC MII Receive (see Figure 1-1 )
          8. 7.11.6.3.8 EMAC MII Receive Timing Diagram
        4. 7.11.6.4 MDIO Electrical Data and Timing
          1. 7.11.6.4.1 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for MDIO_CK (see Figure 1-1 )
          2. 7.11.6.4.2 MDIO_CK Timing Diagram
          3. 7.11.6.4.3 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for MDIO as Output (see Figure 1-1 )
          4. 7.11.6.4.4 MDIO as Output Timing Diagram
          5. 7.11.6.4.5 Timing Requirements for MDIO as Input (see Figure 1-1 )
          6. 7.11.6.4.6 MDIO as Input Timing Diagram
    12. 7.12 Control Subsystem Peripherals
      1. 7.12.1 High-Resolution PWM and Enhanced PWM Modules
        1. 7.12.1.1 HRPWM Electrical Data and Timing
          1. 7.12.1.1.1 High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz)
        2. 7.12.1.2 ePWM Electrical Data and Timing
          1. 7.12.1.2.1 ePWM Timing Requirements
          2. 7.12.1.2.2 ePWM Switching Characteristics
          3. 7.12.1.2.3 Trip-Zone Input Timing
            1. 7.12.1.2.3.1 Trip-Zone Input Timing Requirements
      2. 7.12.2 Enhanced Capture Module
        1. 7.12.2.1 eCAP Electrical Data and Timing
          1. 7.12.2.1.1 eCAP Timing Requirement
          2. 7.12.2.1.2 eCAP Switching Characteristics
      3. 7.12.3 Enhanced Quadrature Encoder Pulse Module
        1. 7.12.3.1 eQEP Electrical Data and Timing
          1. 7.12.3.1.1 eQEP Timing Requirements
          2. 7.12.3.1.2 eQEP Switching Characteristics
      4. 7.12.4 C28x Inter-Integrated Circuit Module
        1. 7.12.4.1 Functional Overview
        2. 7.12.4.2 Clock Generation
        3. 7.12.4.3 I2C Electrical Data and Timing
          1. 7.12.4.3.1 I2C Timing
      5. 7.12.5 C28x Serial Communications Interface
        1. 7.12.5.1 Architecture
        2. 7.12.5.2 Multiprocessor and Asynchronous Communication Modes
      6. 7.12.6 C28x Serial Peripheral Interface
        1. 7.12.6.1 Functional Overview
        2. 7.12.6.2 SPI Electrical Data and Timing
          1. 7.12.6.2.1 Master Mode Timing
            1. 7.12.6.2.1.1 SPI Master Mode External Timing (Clock Phase = 0)
            2. 7.12.6.2.1.2 SPI Master Mode External Timing (Clock Phase = 1)
          2. 7.12.6.2.2 Slave Mode Timing
            1. 7.12.6.2.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
            2. 7.12.6.2.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
      7. 7.12.7 C28x Multichannel Buffered Serial Port
        1. 7.12.7.1 McBSP Electrical Data and Timing
          1. 7.12.7.1.1 McBSP Transmit and Receive Timing
            1. 7.12.7.1.1.1 McBSP Timing Requirements
            2. 7.12.7.1.1.2 McBSP Switching Characteristics
            3. 7.12.7.1.1.3 McBSP Timing Diagrams
          2. 7.12.7.1.2 McBSP as SPI Master or Slave Timing
            1. 7.12.7.1.2.1  McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. 7.12.7.1.2.2  McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 10b, CLKXP = 0)
            3. 7.12.7.1.2.3  McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 Timing Diagram
            4. 7.12.7.1.2.4  McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            5. 7.12.7.1.2.5  McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 11b, CLKXP = 0)
            6. 7.12.7.1.2.6  McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 Timing Diagram
            7. 7.12.7.1.2.7  McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            8. 7.12.7.1.2.8  McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 10b, CLKXP = 1)
            9. 7.12.7.1.2.9  McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 Timing Diagram
            10. 7.12.7.1.2.10 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            11. 7.12.7.1.2.11 McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 11b, CLKXP = 1)
            12. 7.12.7.1.2.12 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 Timing Diagram
  8. 8 Detailed Description
    1. 8.1  Memory Maps
      1. 8.1.1 Control Subsystem Memory Map
      2. 8.1.2 Master Subsystem Memory Map
    2. 8.2  Identification
    3. 8.3  Master Subsystem
      1. 8.3.1 Cortex-M3 CPU
      2. 8.3.2 Cortex-M3 DMA and NVIC
      3. 8.3.3 Cortex-M3 Interrupts
      4. 8.3.4 Cortex-M3 Vector Table
      5. 8.3.5 Cortex-M3 Local Peripherals
      6. 8.3.6 Cortex-M3 Local Memory
      7. 8.3.7 Cortex-M3 Accessing Shared Resources and Analog Peripherals
    4. 8.4  Control Subsystem
      1. 8.4.1 C28x CPU/FPU/VCU
      2. 8.4.2 C28x Core Hardware Built-In Self-Test
      3. 8.4.3 C28x Peripheral Interrupt Expansion
      4. 8.4.4 C28x Direct Memory Access
      5. 8.4.5 C28x Local Peripherals
      6. 8.4.6 C28x Local Memory
      7. 8.4.7 C28x Accessing Shared Resources and Analog Peripherals
    5. 8.5  Analog Subsystem
      1. 8.5.1 ADC1
      2. 8.5.2 ADC2
      3. 8.5.3 Analog Comparator + DAC
      4. 8.5.4 Analog Common Interface Bus
    6. 8.6  Master Subsystem NMIs
    7. 8.7  Control Subsystem NMIs
    8. 8.8  Resets
      1. 8.8.1 Cortex-M3 Resets
      2. 8.8.2 C28x Resets
      3. 8.8.3 Analog Subsystem and Shared Resources Resets
      4. 8.8.4 Device Boot Sequence
    9. 8.9  Internal Voltage Regulation and Power-On-Reset Functionality
      1. 8.9.1 Analog Subsystem: Internal 1.8-V VREG
      2. 8.9.2 Digital Subsystem: Internal 1.2-V VREG
      3. 8.9.3 Analog and Digital Subsystems: Power-On-Reset Functionality
      4. 8.9.4 Connecting ARS and XRS Pins
    10. 8.10 Input Clocks and PLLs
      1. 8.10.1 Internal Oscillator (Zero-Pin)
      2. 8.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC)
      3. 8.10.3 External Oscillators (Pins X1 and XCLKIN)
      4. 8.10.4 Main PLL
      5. 8.10.5 USB PLL
    11. 8.11 Master Subsystem Clocking
      1. 8.11.1 Cortex-M3 Run Mode
      2. 8.11.2 Cortex-M3 Sleep Mode
      3. 8.11.3 Cortex-M3 Deep Sleep Mode
    12. 8.12 Control Subsystem Clocking
      1. 8.12.1 C28x Normal Mode
      2. 8.12.2 C28x IDLE Mode
      3. 8.12.3 C28x STANDBY Mode
    13. 8.13 Analog Subsystem Clocking
    14. 8.14 Shared Resources Clocking
    15. 8.15 Loss of Input Clock (NMI Watchdog Function)
    16. 8.16 GPIOs and Other Pins
      1. 8.16.1 GPIO_MUX1
      2. 8.16.2 GPIO_MUX2
      3. 8.16.3 AIO_MUX1
      4. 8.16.4 AIO_MUX2
    17. 8.17 Emulation/JTAG
    18. 8.18 Code Security Module
      1. 8.18.1 Functional Description
    19. 8.19 µCRC Module
      1. 8.19.1 Functional Description
      2. 8.19.2 CRC Polynomials
      3. 8.19.3 CRC Calculation Procedure
      4. 8.19.4 CRC Calculation for Data Stored In Secure Memory
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Device and Development Support Tool Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Trademarks
    5. 10.5 サポート・リソース
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.1 Control Subsystem Memory Map

Table 8-1 Control Subsystem M0, M1 RAM
C DMA ACCESS(1) C ADDRESS
(x16 ALIGNED)(1)		 CONTROL SUBSYSTEM M0, M1 RAM SIZE
(BYTES)
no 0000 0000 – 0000 03FF M0 RAM (ECC) 2K
no 0000 0400 – 0000 07FF M1 RAM (ECC) 2K
(1) The letter "C" refers to the Control Subsystem.
Table 8-2 Control Subsystem Peripheral Frame 0
C DMA ACCESS(1) C ADDRESS
(x16 ALIGNED)(1)		 CONTROL SUBSYSTEM PERIPHERAL FRAME 0
(INCLUDES ANALOG)		 SIZE
(BYTES)
0000 0800 – 0000 087F Reserved
no 0000 0880 – 0000 0890 Control Subsystem Device Configuration Registers (Read Only) 34
0000 0891 – 0000 0ADF Reserved
no 0000 0AE0 – 0000 0AEF C28x CSM Registers 32
0000 0AF0 – 0000 0AFF Reserved
yes 0000 0B00 – 0000 0B0F ADC1 Result Registers 32
0000 0B10 – 0000 0B3F Reserved
yes 0000 0B40 – 0000 0B4F ADC2 Result Registers 32
0000 0B50 – 0000 0BFF Reserved
no 0000 0C00 – 0000 0C07 CPU Timer 0 16
no 0000 0C08 – 0000 0C0F CPU Timer 1 16
no 0000 0C10 – 0000 0C17 CPU Timer 2 16
0000 0C18 – 0000 0CDF Reserved
no 0000 0CE0 – 0000 0CFF PIE Registers 64
no 0000 0D00 – 0000 0DFF PIE Vector Table 512
no 0000 0E00 – 0000 0EFF PIE Vector Table Copy (Read Only) 512
0000 0F00 – 0000 0FFF Reserved
no 0000 1000 – 0000 11FF C28x DMA Registers 1K
0000 1200 – 0000 16FF Reserved
no 0000 1700 – 0000 177F Analog Subsystem Control Registers 256
no 0000 1780 – 0000 17FF Hardware BIST Registers 256
0000 1800 – 0000 3FFF Reserved
(1) The letter "C" refers to the Control Subsystem.
Table 8-3 Control Subsystem Peripheral Frame 3
C DMA ACCESS(1) C ADDRESS
(x16 ALIGNED)(1)		 CONTROL SUBSYSTEM
PERIPHERAL FRAME 3		 SIZE
(BYTES)		 M ADDRESS
(BYTE-ALIGNED)(2)		 µDMA ACCESS
no 0000 4000 – 0000 4181 C28x Flash Control Registers 772
0000 4182 – 0000 42FF Reserved
no 0000 4300 – 0000 4323 C28x Flash ECC Error Log Registers 72
0000 4324 – 0000 43FF Reserved
no 0000 4400 – 0000 443F M Clock Control Registers(2) 128 400F B800 – 400F B87F no
0000 4440 – 0000 48FF Reserved
no 0000 4900 – 0000 497F RAM Configuration Registers 256 400F B200 – 400F B2FF no
0000 4980 – 0000 49FF Reserved
no 0000 4A00 – 0000 4A7F RAM ECC/Parity/Access Error Log Registers 256 400F B300 – 400F B3FF no
0000 4A80 – 0000 4DFF Reserved
no 0000 4E00 – 0000 4E3F CtoM and MtoC IPC Registers 128 400F B700 – 400F B77F no
0000 4E40 – 0000 4FFF Reserved
yes 0000 5000 – 0000 503F McBSP-A 128
0000 5040 – 0000 50FF Reserved
yes 0000 5100 – 0000 517F EPWM1 (Hi-Resolution) 256
yes 0000 5180 – 0000 51FF EPWM2 (Hi-Resolution) 256
yes 0000 5200 – 0000 527F EPWM3 (Hi-Resolution) 256
yes 0000 5280 – 0000 52FF EPWM4 (Hi-Resolution) 256
yes 0000 5300 – 0000 537F EPWM5 (Hi-Resolution) 256
yes 0000 5380 – 0000 53FF EPWM6 (Hi-Resolution) 256
yes 0000 5400 – 0000 547F EPWM7 (Hi-Resolution) 256
yes 0000 5480 – 0000 54FF EPWM8 (Hi-Resolution) 256
yes 0000 5500 – 0000 557F EPWM9 256
0000 5580 – 0000 57FF Reserved
(1) The letter "C" refers to the Control Subsystem.
(2) The letter "M" refers to the Master Subsystem.
Table 8-4 Control Subsystem Peripheral Frame 1
C DMA ACCESS(1) C ADDRESS
(x16 ALIGNED)(1)		 CONTROL SUBSYSTEM PERIPHERAL FRAME 1 SIZE
(BYTES)
0000 5800 – 0000 59FF Reserved
no 0000 5A00 – 0000 5A1F ECAP1 64
no 0000 5A20 – 0000 5A3F ECAP2 64
no 0000 5A40 – 0000 5A5F ECAP3 64
no 0000 5A60 – 0000 5A7F ECAP4 64
no 0000 5A80 – 0000 5A9F ECAP5 64
no 0000 5AA0 – 0000 5ABF ECAP6 64
0000 5AC0 – 0000 5AFF Reserved
no 0000 5B00 – 0000 5B3F EQEP1 128
no 0000 5B40 – 0000 5B7F EQEP2 128
no 0000 5B80 – 0000 5BBF EQEP3 128
0000 5BC0 – 0000 5F7F Reserved
no 0000 5F80 – 0000 5FFF C GPIO Group 1 Registers(1) 256
0000 6000 – 0000 63FF Reserved
no 0000 6400 – 0000 641F COMP1 Registers 64
no 0000 6420 – 0000 643F COMP2 Registers 64
no 0000 6440 – 0000 645F COMP3 Registers 64
no 0000 6460 – 0000 647F COMP4 Registers 64
no 0000 6480 – 0000 649F COMP5 Registers 64
no 0000 64A0 – 0000 64BF COMP6 Registers 64
0000 64C0 – 0000 6F7F Reserved
no 0000 6F80 – 0000 6FFF C GPIO Group 2 Registers and AIO Mux Registers(1) 256
(1) The letter "C" refers to the Control Subsystem.
Table 8-5 Control Subsystem Peripheral Frame 2
C DMA ACCESS(1) C ADDRESS
(x16 ALIGNED)(1)		 CONTROL SUBSYSTEM PERIPHERAL FRAME 2 SIZE
(BYTES)
0000 7000 – 0000 70FF Reserved
no 0000 7010 – 0000 702F C28x System Control Registers 64
0000 7030 – 0000 703F Reserved
no 0000 7040 – 0000 704F SPI-A 32
no 0000 7050 – 0000 705F SCI-A 32
no 0000 7060 – 0000 706F NMI Watchdog Interrupt Registers 32
no 0000 7070 – 0000 707F External Interrupt Registers 32
0000 7080 – 0000 70FF Reserved
no 0000 7100 – 0000 717F ADC1 Configuration Registers
(Only 16-bit read/write access supported)		 256
no 0000 7180 – 0000 71FF ADC2 Configuration Registers
(Only 16-bit read/write access supported)		 256
0000 7200 – 0000 78FF Reserved
no 0000 7900 – 0000 793F I2C-A 128
0000 7940 – 0000 7FFF Reserved
(1) The letter "C" refers to the Control Subsystem.
Table 8-6 Control Subsystem RAMs
C DMA ACCESS(1) C ADDRESS
(x16 ALIGNED)(1)		 CONTROL SUBSYSTEM RAMS SIZE
(BYTES)		 M ADDRESS
(BYTE-ALIGNED)(2)		 µDMA ACCESS
no 0000 8000 – 0000 8FFF L0 RAM (ECC, Secure) 8K
no 0000 9000 – 0000 9FFF L1 RAM (ECC, Secure) 8K
yes 0000 A000 – 0000 AFFF L2 RAM (Parity, Interleaving) 8K
yes 0000 B000 – 0000 BFFF L3 RAM (Parity, Interleaving) 8K
yes 0000 C000 – 0000 CFFF S0 RAM (Parity, Shared) 8K 2000 8000 – 2000 9FFF yes
yes 0000 D000 – 0000 DFFF S1 RAM (Parity, Shared) 8K 2000 A000 – 2000 BFFF yes
yes 0000 E000 – 0000 EFFF S2 RAM (Parity, Shared) 8K 2000 C000 – 2000 DFFF yes
yes 0000 F000 – 0000 FFFF S3 RAM (Parity, Shared) 8K 2000 E000 – 2000 FFFF yes
yes 0001 0000 – 0001 0FFF S4 RAM (Parity, Shared) 8K 2001 0000 – 2001 1FFF yes
yes 0001 1000 – 0001 1FFF S5 RAM (Parity, Shared) 8K 2001 2000 – 2001 3FFF yes
yes 0001 2000 – 0001 2FFF S6 RAM (Parity, Shared) 8K 2001 4000 – 2001 5FFF yes
yes 0001 3000 – 0001 3FFF S7 RAM (Parity, Shared) 8K 2001 6000 – 2001 7FFF yes
0001 4000 – 0003 F7FF Reserved
yes 0003 F800 – 0003 FBFF CtoM MSG RAM (Parity) 2K 2007 F000 – 2007 F7FF yes
read only
yes
read only		 0003 FC00 – 0003 FFFF MtoC MSG RAM (Parity) 2K 2007 F800 – 2007 FFFF yes
0004 0000 – 0004 7FFF Reserved
no 0004 8000 – 0004 8FFF L0 RAM - ECC Bits 8K
no 0004 9000 – 0004 9FFF L1 RAM - ECC Bits 8K
no 0004 A000 – 0004 AFFF L2 RAM - Parity Bits 8K
no 0004 B000 – 0004 BFFF L3 RAM - Parity Bits 8K
no 0004 C000 – 0004 CFFF S0 RAM - Parity Bits 8K 2008 8000 – 2008 9FFF no
no 0004 D000 – 0004 DFFF S1 RAM - Parity Bits 8K 2008 A000 – 2008 BFFF no
no 0004 E000 – 0004 EFFF S2 RAM - Parity Bits 8K 2008 C000 – 2008 DFFF no
no 0004 F000 – 0004 FFFF S3 RAM - Parity Bits 8K 2008 E000 – 2008 FFFF no
no 0005 0000 – 0005 0FFF S4 RAM - Parity Bits 8K 2009 0000 – 2009 1FFF no
no 0005 1000 – 0005 1FFF S5 RAM - Parity Bits 8K 2009 2000 – 2009 3FFF no
no 0005 2000 – 0005 2FFF S6 RAM - Parity Bits 8K 2009 4000 – 2009 5FFF no
no 0005 3000 – 0005 3FFF S7 RAM - Parity Bits 8K 2009 6000 – 2009 7FFF no
0005 4000 – 0007 EFFF Reserved
no 0007 F000 – 0007 F3FF M0 RAM - ECC Bits 2K
no 0007 F400 – 0007 F7FF M1 RAM - ECC Bits 2K
no 0007 F800 – 0007 FBFF CtoM MSG RAM - Parity Bits 2K 200F F000 – 200F F7FF no
no 0007 FC00 – 0007 FFFF MtoC MSG RAM - Parity Bits 2K 200F F800 – 200F FFFF no
0008 0000 – 0009 FFFF Reserved
(1) The letter "C" refers to the Control Subsystem.
(2) The letter "M" refers to the Master Subsystem.
Table 8-7 Control Subsystem Flash, ECC, OTP, Boot ROM
C DMA ACCESS(1) C ADDRESS
(x16 ALIGNED)(1)		 CONTROL SUBSYSTEM
FLASH, ECC, OTP,
BOOT ROM		 SIZE
(BYTES)		 M ADDRESS
(BYTE-ALIGNED)(2)		 µDMA ACCESS
no 0010 0000 – 0010 1FFF Sector N (not available for 256KB Flash configuration) 16K
no 0010 2000 – 0010 3FFF Sector M (not available for 256KB Flash configuration) 16K
no 0010 4000 – 0010 5FFF Sector L (not available for 256KB Flash configuration) 16K
no 0010 6000 – 0010 7FFF Sector K (not available for 256KB Flash configuration) 16K
no 0010 8000 – 0010 FFFF Sector J (not available for 256KB Flash configuration) 64K
no 0011 0000 – 0011 7FFF Sector I (not available for 256KB Flash configuration) 64K
no 0011 8000 – 0011 FFFF Sector H (not available for 256KB Flash configuration) 64K
no 0012 0000 – 0012 7FFF Sector G 64K
no 0012 8000 – 0012 FFFF Sector F 64K
no 0013 0000 – 0013 7FFF Sector E 64K
no 0013 8000 – 0013 9FFF Sector D 16K
no 0013 A000 – 0013 BFFF Sector C 16K
no 0013 C000 – 0013 DFFF Sector B 16K
no 0013 E000 – 0013 FFFF Sector A
(CSM password in the high address)		 16K
0014 0000 – 001F FFFF Reserved
no 0020 0000 – 0020 7FFF Flash - ECC Bits
(1/8 of Flash used = 64KB)		 64K
0020 8000 – 0024 01FF Reserved
no 0024 0200 – 0024 03FF TI one-time programmable (OTP) memory 1K
0024 0400 – 002F FFFF Reserved
yes 0030 0000 – 003F 7FFF EPI0
(External Peripheral/Memory Interface)(3)		 2M(4) 6000 0000 – DFFF FFFF yes
no 003F 8000 – 003F FFFF C28x Boot ROM (64KB) 64K
(1) The letter "C" refers to the Control Subsystem.
(2) The letter "M" refers to the Master Subsystem.
(3) The Control Subsystem has no direct access to EPI in silicon revision 0 devices.
(4) The Control Subsystem has less address reach to EPI memory than the Master Subsystem.