JAJSJA4L June   2011  – February 2021 F28M35E20B , F28M35H22C , F28M35H52C , F28M35H52C-Q1 , F28M35M22C , F28M35M52C

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1. 3.1 機能ブロック図
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
      1. 6.2.1 Signal Descriptions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Automotive
    3. 7.3  ESD Ratings – Commercial
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK
      2. 7.5.2 Current Consumption at 100-MHz C28x SYSCLKOUT and 100-MHz M3SSCLK
      3. 7.5.3 Current Consumption at 75-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK
      4. 7.5.4 Current Consumption at 60-MHz C28x SYSCLKOUT and 60-MHz M3SSCLK
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics for RFP PowerPAD Package
    8. 7.8  Thermal Design Considerations
    9. 7.9  Timing and Switching Characteristics
      1. 7.9.1 Power Sequencing
        1. 7.9.1.1 Reset ( XRS) Timing Requirements
        2. 7.9.1.2 Reset ( XRS) Switching Characteristics
        3. 7.9.1.3 Power Management and Supervisory Circuit Solutions
      2. 7.9.2 Clock Specifications
        1. 7.9.2.1 Changing the Frequency of the Main PLL
        2. 7.9.2.2 Input Clock Frequency and Timing Requirements, PLL Lock Times
          1. 7.9.2.2.1 Input Clock Frequency
          2. 7.9.2.2.2 Crystal Oscillator Electrical Characteristics
          3. 7.9.2.2.3 X1 Timing Requirements - PLL Enabled (1)
          4. 7.9.2.2.4 X1 Timing Requirements - PLL Disabled
          5. 7.9.2.2.5 XCLKIN Timing Requirements - PLL Enabled
          6. 7.9.2.2.6 XCLKIN Timing Requirements - PLL Disabled
          7. 7.9.2.2.7 PLL Lock Times
        3. 7.9.2.3 Output Clock Frequency and Switching Characteristics
          1. 7.9.2.3.1 Output Clock Frequency
          2. 7.9.2.3.2 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (1)
        4. 7.9.2.4 Internal Clock Frequencies
          1. 7.9.2.4.1 Internal Clock Frequencies (150-MHz Devices)
      3. 7.9.3 Timing Parameter Symbology
        1. 7.9.3.1 General Notes on Timing Parameters
        2. 7.9.3.2 Test Load Circuit
      4. 7.9.4 Flash Timing – Master Subsystem
        1. 7.9.4.1 Master Subsystem – Flash/OTP Endurance
        2. 7.9.4.2 Master Subsystem – Flash Parameters
        3. 7.9.4.3 Master Subsystem – Flash/OTP Access Timing
        4. 7.9.4.4 Master Subsystem – Flash Data Retention Duration
        5. 7.9.4.5 Master Subsystem – Minimum Required Flash/OTP Wait States at Different Frequencies
      5. 7.9.5 Flash Timing – Control Subsystem
        1. 7.9.5.1 Control Subsystem – Flash/OTP Endurance
        2. 7.9.5.2 Control Subsystem – Flash Parameters
        3. 7.9.5.3 Control Subsystem – Flash/OTP Access Timing
        4. 7.9.5.4 Control Subsystem – Flash Data Retention Duration
      6. 7.9.6 GPIO Electrical Data and Timing
        1. 7.9.6.1 GPIO - Output Timing
          1. 7.9.6.1.1 General-Purpose Output Switching Characteristics
        2. 7.9.6.2 GPIO - Input Timing
          1. 7.9.6.2.1 General-Purpose Input Timing Requirements
        3. 7.9.6.3 Sampling Window Width for Input Signals
        4. 7.9.6.4 Low-Power Mode Wakeup Timing
          1. 7.9.6.4.1 IDLE Mode Timing Requirements
          2. 7.9.6.4.2 IDLE Mode Switching Characteristics
          3. 7.9.6.4.3 IDLE Entry and Exit Timing Diagram
          4. 7.9.6.4.4 STANDBY Mode Timing Requirements
          5. 7.9.6.4.5 STANDBY Mode Switching Characteristics
          6. 7.9.6.4.6 STANDBY Entry and Exit Timing Diagram
          7. 7.9.6.4.7 HALT Mode Timing Requirements
          8. 7.9.6.4.8 HALT Mode Switching Characteristics
          9. 7.9.6.4.9 HALT Entry and Exit Timing Diagram
      7. 7.9.7 External Interrupt Electrical Data and Timing
        1. 7.9.7.1 External Interrupt Timing Requirements
        2. 7.9.7.2 External Interrupt Switching Characteristics
        3. 7.9.7.3 External Interrupt Timing Diagram
    10. 7.10 Analog and Shared Peripherals
      1. 7.10.1 Analog-to-Digital Converter
        1. 7.10.1.1 Sample Mode
        2. 7.10.1.2 Start-of-Conversion Triggers
        3. 7.10.1.3 Analog Inputs
        4. 7.10.1.4 ADC Result Registers and EOC Interrupts
        5. 7.10.1.5 ADC Electrical Data and Timing
          1. 7.10.1.5.1 ADC Electrical Characteristics
          2. 7.10.1.5.2 External ADC Start-of-Conversion Switching Characteristics
          3. 7.10.1.5.3 ADCSOCAO or ADCSOCBO Timing Diagram
      2. 7.10.2 Comparator + DAC Units
        1. 7.10.2.1 On-Chip Comparator and DAC Electrical Data and Timing
          1. 7.10.2.1.1 Electrical Characteristics of the Comparator/DAC
      3. 7.10.3 Interprocessor Communications
      4. 7.10.4 External Peripheral Interface
        1. 7.10.4.1 EPI General-Purpose Mode
        2. 7.10.4.2 EPI SDRAM Mode
        3. 7.10.4.3 EPI Host Bus Mode
          1. 7.10.4.3.1 EPI 8-Bit Host Bus (HB-8) Mode
            1. 7.10.4.3.1.1 HB-8 Muxed Address/Data Mode
            2. 7.10.4.3.1.2 HB-8 Non-Muxed Address/Data Mode
            3. 7.10.4.3.1.3 HB-8 FIFO Mode
          2. 7.10.4.3.2 EPI 16-Bit Host Bus (HB-16) Mode
            1. 7.10.4.3.2.1 HB-16 Muxed Address/Data Mode
            2. 7.10.4.3.2.2 HB-16 Non-Muxed Address/Data Mode
            3. 7.10.4.3.2.3 HB-16 FIFO Mode
        4. 7.10.4.4 EPI Electrical Data and Timing
          1. 7.10.4.4.1 EPI SDRAM Interface Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (see Figure 1-1 , Figure 1-1 , and Figure 1-1 )
          2. 7.10.4.4.2 EPI SDRAM Timing Diagrams
          3. 7.10.4.4.3 EPI Host-Bus 8 and Host-Bus 16 Interface Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (see Figure 1-1 , Figure 1-1 , Figure 1-1 , and Figure 1-1 )
          4. 7.10.4.4.4 EPI Host-Bus 8 and Host-Bus 16 Interface Timing Requirements (1) (see Figure 1-1 and Figure 1-1 )
          5. 7.10.4.4.5 EPI Host-Bus 8/16 Mode Timing Diagrams
          6. 7.10.4.4.6 EPI General-Purpose Interface Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (see Figure 1-1 )
          7. 7.10.4.4.7 EPI General-Purpose Interface Timing Requirements (see Figure 1-1 and Figure 1-1 )
          8. 7.10.4.4.8 EPI General-Purpose Interface Timing Diagrams
    11. 7.11 Master Subsystem Peripherals
      1. 7.11.1 Synchronous Serial Interface
        1. 7.11.1.1 Bit Rate Generation
        2. 7.11.1.2 Transmit FIFO
        3. 7.11.1.3 Receive FIFO
        4. 7.11.1.4 Interrupts
        5. 7.11.1.5 Frame Formats
      2. 7.11.2 Universal Asynchronous Receiver/Transmitter
        1. 7.11.2.1 Baud-Rate Generation
        2. 7.11.2.2 Transmit and Receive Logic
        3. 7.11.2.3 Data Transmission and Reception
        4. 7.11.2.4 Interrupts
      3. 7.11.3 Cortex-M3 Inter-Integrated Circuit
        1. 7.11.3.1 Functional Overview
        2. 7.11.3.2 Available Speed Modes
        3. 7.11.3.3 I2C Electrical Data and Timing
          1. 7.11.3.3.1 I2C Timing
      4. 7.11.4 Cortex-M3 Controller Area Network
        1. 7.11.4.1 Functional Overview
      5. 7.11.5 Cortex-M3 Universal Serial Bus Controller
        1. 7.11.5.1 Functional Description
      6. 7.11.6 Cortex-M3 Ethernet Media Access Controller
        1. 7.11.6.1 Functional Overview
        2. 7.11.6.2 MII Signals
        3. 7.11.6.3 EMAC Electrical Data and Timing
          1. 7.11.6.3.1 Timing Requirements for MIITXCK (see Figure 1-1 )
          2. 7.11.6.3.2 MIITXCK Timing Diagrams
          3. 7.11.6.3.3 Timing Requirements for MIIRXCK (see Figure 1-1 )
          4. 7.11.6.3.4 MIIRXCK Timing Diagram
          5. 7.11.6.3.5 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for EMAC MII Transmit (see Figure 1-1 )
          6. 7.11.6.3.6 EMAC MII Transmit Timing Diagram
          7. 7.11.6.3.7 Timing Requirements for EMAC MII Receive (see Figure 1-1 )
          8. 7.11.6.3.8 EMAC MII Receive Timing Diagram
        4. 7.11.6.4 MDIO Electrical Data and Timing
          1. 7.11.6.4.1 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for MDIO_CK (see Figure 1-1 )
          2. 7.11.6.4.2 MDIO_CK Timing Diagram
          3. 7.11.6.4.3 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for MDIO as Output (see Figure 1-1 )
          4. 7.11.6.4.4 MDIO as Output Timing Diagram
          5. 7.11.6.4.5 Timing Requirements for MDIO as Input (see Figure 1-1 )
          6. 7.11.6.4.6 MDIO as Input Timing Diagram
    12. 7.12 Control Subsystem Peripherals
      1. 7.12.1 High-Resolution PWM and Enhanced PWM Modules
        1. 7.12.1.1 HRPWM Electrical Data and Timing
          1. 7.12.1.1.1 High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz)
        2. 7.12.1.2 ePWM Electrical Data and Timing
          1. 7.12.1.2.1 ePWM Timing Requirements
          2. 7.12.1.2.2 ePWM Switching Characteristics
          3. 7.12.1.2.3 Trip-Zone Input Timing
            1. 7.12.1.2.3.1 Trip-Zone Input Timing Requirements
      2. 7.12.2 Enhanced Capture Module
        1. 7.12.2.1 eCAP Electrical Data and Timing
          1. 7.12.2.1.1 eCAP Timing Requirement
          2. 7.12.2.1.2 eCAP Switching Characteristics
      3. 7.12.3 Enhanced Quadrature Encoder Pulse Module
        1. 7.12.3.1 eQEP Electrical Data and Timing
          1. 7.12.3.1.1 eQEP Timing Requirements
          2. 7.12.3.1.2 eQEP Switching Characteristics
      4. 7.12.4 C28x Inter-Integrated Circuit Module
        1. 7.12.4.1 Functional Overview
        2. 7.12.4.2 Clock Generation
        3. 7.12.4.3 I2C Electrical Data and Timing
          1. 7.12.4.3.1 I2C Timing
      5. 7.12.5 C28x Serial Communications Interface
        1. 7.12.5.1 Architecture
        2. 7.12.5.2 Multiprocessor and Asynchronous Communication Modes
      6. 7.12.6 C28x Serial Peripheral Interface
        1. 7.12.6.1 Functional Overview
        2. 7.12.6.2 SPI Electrical Data and Timing
          1. 7.12.6.2.1 Master Mode Timing
            1. 7.12.6.2.1.1 SPI Master Mode External Timing (Clock Phase = 0)
            2. 7.12.6.2.1.2 SPI Master Mode External Timing (Clock Phase = 1)
          2. 7.12.6.2.2 Slave Mode Timing
            1. 7.12.6.2.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
            2. 7.12.6.2.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
      7. 7.12.7 C28x Multichannel Buffered Serial Port
        1. 7.12.7.1 McBSP Electrical Data and Timing
          1. 7.12.7.1.1 McBSP Transmit and Receive Timing
            1. 7.12.7.1.1.1 McBSP Timing Requirements
            2. 7.12.7.1.1.2 McBSP Switching Characteristics
            3. 7.12.7.1.1.3 McBSP Timing Diagrams
          2. 7.12.7.1.2 McBSP as SPI Master or Slave Timing
            1. 7.12.7.1.2.1  McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. 7.12.7.1.2.2  McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 10b, CLKXP = 0)
            3. 7.12.7.1.2.3  McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 Timing Diagram
            4. 7.12.7.1.2.4  McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            5. 7.12.7.1.2.5  McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 11b, CLKXP = 0)
            6. 7.12.7.1.2.6  McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 Timing Diagram
            7. 7.12.7.1.2.7  McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            8. 7.12.7.1.2.8  McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 10b, CLKXP = 1)
            9. 7.12.7.1.2.9  McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 Timing Diagram
            10. 7.12.7.1.2.10 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            11. 7.12.7.1.2.11 McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 11b, CLKXP = 1)
            12. 7.12.7.1.2.12 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 Timing Diagram
  8. 8 Detailed Description
    1. 8.1  Memory Maps
      1. 8.1.1 Control Subsystem Memory Map
      2. 8.1.2 Master Subsystem Memory Map
    2. 8.2  Identification
    3. 8.3  Master Subsystem
      1. 8.3.1 Cortex-M3 CPU
      2. 8.3.2 Cortex-M3 DMA and NVIC
      3. 8.3.3 Cortex-M3 Interrupts
      4. 8.3.4 Cortex-M3 Vector Table
      5. 8.3.5 Cortex-M3 Local Peripherals
      6. 8.3.6 Cortex-M3 Local Memory
      7. 8.3.7 Cortex-M3 Accessing Shared Resources and Analog Peripherals
    4. 8.4  Control Subsystem
      1. 8.4.1 C28x CPU/FPU/VCU
      2. 8.4.2 C28x Core Hardware Built-In Self-Test
      3. 8.4.3 C28x Peripheral Interrupt Expansion
      4. 8.4.4 C28x Direct Memory Access
      5. 8.4.5 C28x Local Peripherals
      6. 8.4.6 C28x Local Memory
      7. 8.4.7 C28x Accessing Shared Resources and Analog Peripherals
    5. 8.5  Analog Subsystem
      1. 8.5.1 ADC1
      2. 8.5.2 ADC2
      3. 8.5.3 Analog Comparator + DAC
      4. 8.5.4 Analog Common Interface Bus
    6. 8.6  Master Subsystem NMIs
    7. 8.7  Control Subsystem NMIs
    8. 8.8  Resets
      1. 8.8.1 Cortex-M3 Resets
      2. 8.8.2 C28x Resets
      3. 8.8.3 Analog Subsystem and Shared Resources Resets
      4. 8.8.4 Device Boot Sequence
    9. 8.9  Internal Voltage Regulation and Power-On-Reset Functionality
      1. 8.9.1 Analog Subsystem: Internal 1.8-V VREG
      2. 8.9.2 Digital Subsystem: Internal 1.2-V VREG
      3. 8.9.3 Analog and Digital Subsystems: Power-On-Reset Functionality
      4. 8.9.4 Connecting ARS and XRS Pins
    10. 8.10 Input Clocks and PLLs
      1. 8.10.1 Internal Oscillator (Zero-Pin)
      2. 8.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC)
      3. 8.10.3 External Oscillators (Pins X1 and XCLKIN)
      4. 8.10.4 Main PLL
      5. 8.10.5 USB PLL
    11. 8.11 Master Subsystem Clocking
      1. 8.11.1 Cortex-M3 Run Mode
      2. 8.11.2 Cortex-M3 Sleep Mode
      3. 8.11.3 Cortex-M3 Deep Sleep Mode
    12. 8.12 Control Subsystem Clocking
      1. 8.12.1 C28x Normal Mode
      2. 8.12.2 C28x IDLE Mode
      3. 8.12.3 C28x STANDBY Mode
    13. 8.13 Analog Subsystem Clocking
    14. 8.14 Shared Resources Clocking
    15. 8.15 Loss of Input Clock (NMI Watchdog Function)
    16. 8.16 GPIOs and Other Pins
      1. 8.16.1 GPIO_MUX1
      2. 8.16.2 GPIO_MUX2
      3. 8.16.3 AIO_MUX1
      4. 8.16.4 AIO_MUX2
    17. 8.17 Emulation/JTAG
    18. 8.18 Code Security Module
      1. 8.18.1 Functional Description
    19. 8.19 µCRC Module
      1. 8.19.1 Functional Description
      2. 8.19.2 CRC Polynomials
      3. 8.19.3 CRC Calculation Procedure
      4. 8.19.4 CRC Calculation for Data Stored In Secure Memory
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Device and Development Support Tool Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Trademarks
    5. 10.5 サポート・リソース
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.2 Master Subsystem Memory Map

Table 8-8 Master Subsystem Flash, ECC, OTP, Boot ROM
µDMA ACCESS M ADDRESS
(BYTE-ALIGNED)(1)		 MASTER SUBSYSTEM FLASH, ECC, OTP, BOOT ROM SIZE
(BYTES)
no 0000 0000 – 0000 FFFF Boot ROM - Dual-mapped to 0x0100 0000
(Both maps access same physical location.)		 64K
0001 0000 – 001F FFFF Reserved
no 0020 0000 – 0020 3FFF Sector N
(Zone 1 CSM password in the low address.)		 16K
no 0020 4000 – 0020 7FFF Sector M 16K
no 0020 8000 – 0020 BFFF Sector L 16K
no 0020 C000 – 0020 FFFF Sector K 16K
no 0021 0000 – 0021 FFFF Sector J 64K
no 0022 0000 – 0022 FFFF Sector I (not available for 256KB Flash configuration) 64K
no 0023 0000 – 0023 FFFF Sector H (not available for 256KB Flash configuration) 64K
no 0024 0000 – 0024 FFFF Sector G (not available for 256KB Flash configuration) 64K
no 0025 0000 – 0025 FFFF Sector F (not available for 256KB Flash configuration) 64K
no 0026 0000 – 0026 FFFF Sector E 64K
no 0027 0000 – 0027 3FFF Sector D 16K
no 0027 4000 – 0027 7FFF Sector C 16K
no 0027 8000 – 0027 BFFF Sector B 16K
no 0027 C000 – 0027 FFFF Sector A
(Zone 2 CSM password in the high address.)		 16K
0028 0000 – 005F FFFF Reserved
no 0060 0000 – 0060 FFFF Flash - ECC Bits
(1/8 of Flash used = 64KB)		 64K
0061 0000 – 0068 047F Reserved
no 0068 0480 – 0068 07FF TI OTP 896
no 0068 0800 OTP – Security Lock 4
0068 0804 Reserved
0068 0808 Reserved
no 0068 080C OTP – Zone 2 Flash Start Address 4
no 0068 0810 OTP – Ethernet Media Access Controller (EMAC) Address 0 4
no 0068 0814 OTP – EMAC Address 1 4
0068 0818 Reserved
no 0068 081C Main Oscillator Clock Frequency 4
0068 0820 Reserved
no 0068 0824 Alternate Boot mode Pin Configuration 4
0068 0828 Reserved
no 0068 082C OTP ENTRY POINT 4
0068 0830 – 0070 00FF Reserved
no 0070 0100 – 0070 0102 OTP – ECC Bits – Application Use
(1/8 of OTP used = 3 Bytes)		 3
0070 0103 – 00FF FFFF Reserved
no 0100 0000 – 0100 FFFF Boot ROM – Dual-mapped to 0x0000 0000
(Both maps access same physical location.)		 64K
0101 0000 – 03FF FFFF Reserved
no 0400 0000 – 07FF FFFF ROM/Flash/OTP/Boot ROM – Mirror-mapped for µCRC.
Accessing this area of memory by the µCRC peripheral will cause an access in 0000 0000 – 03FF FFFF memory space.
Mirrored boot ROM: 0x0400 0000 – 0x0400 FFFF (Not dual-mapped ROM address)
Mirrored Flash bank: 0x0420 0000 – 0x042F FFFF
Mirrored Flash OTP: 0x0468 0000 – 0x0468 1FFF
(Read cycles from this space cause the µCRC peripheral to continuously update data checksum inside a register, when reading a block of data.)		 64M
0800 0000 – 1FFF FFFF Reserved
(1) The letter "M" refers to the Master Subsystem.
Table 8-9 Master Subsystem RAMs
µDMA ACCESS M ADDRESS
(BYTE-ALIGNED)(1)		 MASTER SUBSYSTEM RAMS SIZE
(BYTES)		 C ADDRESS
(x16 ALIGNED)(2)		 C DMA ACCESS(2)
no 2000 0000 – 2000 1FFF C0 RAM (ECC, Secure) 8K
no 2000 2000 – 2000 3FFF C1 RAM (ECC, Secure) 8K
yes 2000 4000 – 2000 5FFF C2 RAM (Parity) 8K
yes 2000 6000 – 2000 7FFF C3 RAM (Parity) 8K
yes 2000 8000 – 2000 9FFF S0 RAM (Parity, Shared) 8K 0000 C000 – 0000 CFFF yes
yes 2000 A000 – 2000 BFFF S1 RAM (Parity, Shared) 8K 0000 D000 – 0000 DFFF yes
yes 2000 C000 – 2000 DFFF S2 RAM (Parity, Shared) 8K 0000 E000 – 0000 EFFF yes
yes 2000 E000 – 2000 FFFF S3 RAM (Parity, Shared) 8K 0000 F000 – 0000 FFFF yes
yes 2001 0000 – 2001 1FFF S4 RAM (Parity, Shared) 8K 0001 0000 – 0001 0FFF yes
yes 2001 2000 – 2001 3FFF S5 RAM (Parity, Shared) 8K 0001 1000 – 0001 1FFF yes
yes 2001 4000 – 2001 5FFF S6 RAM (Parity, Shared) 8K 0001 2000 – 0001 2FFF yes
yes 2001 6000 – 2001 7FFF S7 RAM (Parity, Shared) 8K 0001 3000 – 0001 3FFF yes
2001 8000 – 2007 EFFF Reserved
yes
read only		 2007 F000 – 2007 F7FF CtoM MSG RAM (Parity) 2K 0003 F800 – 0003 FBFF yes
yes 2007 F800 – 2007 FFFF MtoC MSG RAM (Parity) 2K 0003 FC00 – 0003 FFFF yes
read only
no 2008 0000 – 2008 1FFF C0 RAM - ECC Bits 8K
no 2008 2000 – 2008 3FFF C1 RAM - ECC Bits 8K
no 2008 4000 – 2008 5FFF C2 RAM - Parity Bits 8K
no 2008 6000 – 2008 7FFF C3 RAM - Parity Bits 8K
no 2008 8000 – 2008 9FFF S0 RAM - Parity Bits 8K 0004 C000 – 0004 CFFF no
no 2008 A000 – 2008 BFFF S1 RAM - Parity Bits 8K 0004 D000 – 0004 DFFF no
no 2008 C000 – 2008 DFFF S2 RAM - Parity Bits 8K 0004 E000 – 0004 EFFF no
no 2008 E000 – 2008 FFFF S3 RAM - Parity Bits 8K 0004 F000 – 0004 FFFF no
no 2009 0000 – 2009 1FFF S4 RAM - Parity Bits 8K 0005 0000 – 0005 0FFF no
no 2009 2000 – 2009 3FFF S5 RAM - Parity Bits 8K 0005 1000 – 0005 1FFF no
no 2009 4000 – 2009 5FFF S6 RAM - Parity Bits 8K 0005 2000 – 0005 2FFF no
no 2009 6000 – 2009 7FFF S7 RAM - Parity Bits 8K 0005 3000 – 0005 3FFF no
2009 8000 – 200F EFFF Reserved
no 200F F000 – 200F F7FF CtoM MSG RAM - Parity Bits 2K 0007 F800 – 0007 FBFF no
no 200F F800 – 200F FFFF MtoC MSG RAM - Parity Bits 2K 0007 FC00 – 0007 FFFF no
2010 0000 – 21FF FFFF Reserved
yes 2200 0000 – 23FF FFFF Bit Banded RAM Zone
(Dedicated address for each RAM bit of Cortex-M3 RAM blocks above)		 32M
yes 2400 0000 – 27FF FFFF All RAM Spaces – Mirror-Mapped for µCRC.
Accessing this memory by the µCRC peripheral will cause an access to
2000 0000 – 23FF FFFF memory space.
(Read cycles from this space cause the µCRC peripheral to continuously update data checksum inside a register when reading a block of data.)		 64M
2800 0000 – 3FFF FFFF Reserved
(1) The letter "M" refers to the Master Subsystem.
(2) The letter "C" refers to the Control Subsystem.
Table 8-10 Master Subsystem Peripherals
µDMA ACCESS M ADDRESS
(BYTE-ALIGNED)(1)		 MASTER SUBSYSTEM PERIPHERALS SIZE
(BYTES)		 C ADDRESS
(x16 ALIGNED)(2)		 C DMA ACCESS(2)
yes 4000 0000 – 4000 0FFF Watchdog Timer 0 Registers 4K
yes 4000 1000 – 4000 1FFF Watchdog Timer 1 Registers 4K
4000 2000 – 4000 3FFF Reserved
yes 4000 4000 – 4000 4FFF M GPIO Port A (APB Bus)(1) 4K
yes 4000 5000 – 4000 5FFF M GPIO Port B (APB Bus)(1) 4K
yes 4000 6000 – 4000 6FFF M GPIO Port C (APB Bus)(1) 4K
yes 4000 7000 – 4000 7FFF M GPIO Port D (APB Bus)(1) 4K
yes 4000 8000 – 4000 8FFF SSI0 4K
yes 4000 9000 – 4000 9FFF SSI1 4K
yes 4000 A000 – 4000 AFFF SSI2 4K
yes 4000 B000 – 4000 BFFF SSI3 4K
yes 4000 C000 – 4000 CFFF UART0 4K
yes 4000 D000 – 4000 DFFF UART1 4K
yes 4000 E000 – 4000 EFFF UART2 4K
yes 4000 F000 – 4000 FFFF UART3 4K
yes 4001 0000 – 4001 0FFF UART4 4K
4001 1000 – 4001 FFFF Reserved
no 4002 0000 – 4002 07FF I2C0 Master 2K
no 4002 0800 – 4002 0FFF I2C0 Slave 2K
no 4002 1000 – 4002 17FF I2C1 Master 2K
no 4002 1800 – 4002 1FFF I2C1 Slave 2K
4002 2000 – 4002 3FFF Reserved
yes 4002 4000 – 4002 4FFF M GPIO Port E (APB Bus)(1) 4K
yes 4002 5000 – 4002 5FFF M GPIO Port F (APB Bus)(1) 4K
yes 4002 6000 – 4002 6FFF M GPIO Port G (APB Bus)(1) 4K
yes 4002 7000 – 4002 7FFF M GPIO Port H (APB Bus)(1) 4K
4002 8000 – 4002 FFFF Reserved
yes 4003 0000 – 4003 0FFF GP Timer 0 4K
yes 4003 1000 – 4003 1FFF GP Timer 1 4K
yes 4003 2000 – 4003 2FFF GP Timer 2 4K
yes 4003 3000 – 4003 3FFF GP Timer 3 4K
4003 4000 – 4003 CFFF Reserved
yes 4003 D000 – 4003 DFFF M GPIO Port J (APB Bus)(1) 4K
4003 E000 – 4003 FFFF Reserved
yes 4004 8000 – 4004 8FFF ENET MAC0 4K
4004 9000 – 4004 FFFF Reserved
yes 4005 0000 – 4005 0FFF USB MAC0 4K
4005 1000 – 4005 7FFF Reserved
yes 4005 8000 – 4005 8FFF M GPIO Port A (AHB Bus)(1) 4K
yes 4005 9000 – 4005 9FFF M GPIO Port B (AHB Bus)(1) 4K
yes 4005 A000 – 4005 AFFF M GPIO Port C (AHB Bus)(1) 4K
yes 4005 B000 – 4005 BFFF M GPIO Port D (AHB Bus)(1) 4K
yes 4005 C000 – 4005 CFFF M GPIO Port E (AHB Bus)(1) 4K
yes 4005 D000 – 4005 DFFF M GPIO Port F (AHB Bus)(1) 4K
yes 4005 E000 – 4005 EFFF M GPIO Port G (AHB Bus)(1) 4K
yes 4005 F000 – 4005 FFFF M GPIO Port H (AHB Bus)(1) 4K
yes 4006 0000 – 4006 0FFF M GPIO Port J (AHB Bus)(1) 4K
4006 1000 – 4006 FFFF Reserved
no 4007 0000 – 4007 3FFF CAN0 16K
no 4007 4000 – 4007 7FFF CAN1 16K
4007 8000 – 400C FFFF Reserved
no 400D 0000 – 400D 0FFF EPI0 (Registers only) 4K
400D 1000 – 400F 9FFF Reserved
no 400F A000 – 400F A303 M Flash Control Registers(1) 772
400F A304 – 400F A5FF Reserved
no 400F A600 – 400F A647 M Flash ECC Error Log Registers(1) 72
400F A648 – 400F AFFF Reserved
no 400F B000 – 400F B1FF Reserved
no 400F B200 – 400F B2FF RAM Configuration Registers 256 0000 4900 – 0000 497F no
no 400F B300 – 400F B3FF RAM ECC/Parity/Access Error Log Registers 256 0000 4A00 – 0000 4A7F no
no 400F B400 – 400F B5FF M CSM Registers(1) 512
no 400F B600 – 400F B67F µCRC 128
400F B680 – 400F B6FF Reserved
no 400F B700 – 400F B77F CtoM and MtoC IPC Registers 128 0000 4E00 – 0000 4E3F no
400F B780 – 400F B7FF Reserved
no 400F B800 – 400F B87F M Clock Control Registers(1) 128 0000 4400 – 0000 443F no
no 400F B880 – 400F B8BF M LPM Control Registers(1) 64
no 400F B8C0 – 400F B8FF M Reset Control Registers(1) 64
no 400F B900 – 400F B93F Device Configuration Registers 64 0000 0880 – 0000 0890 (Read Only)
400F B940 – 400F B97F Reserved
no 400F B980 – 400F B9FF M Write Protect Registers(1) 128
no 400F BA00 – 400F BA7F M NMI Registers(1) 128
400F BA80 – 400F BAFF Reserved
no 400F BB00 – 400F BBFF Reserved
400F BC00 – 400F EFFF Reserved
no 400F F000 – 400F FFFF µDMA Registers 4K
4010 0000 – 41FF FFFF Reserved
yes 4200 0000 – 43FF FFFF Bit Banded Peripheral Zone
(Dedicated address for each register bit of Cortex-M3 peripherals above.)		 32M
4400 0000 – 4FFF FFFF Reserved
(1) The letter "M" refers to the Master Subsystem.
(2) The letter "C" refers to the Control Subsystem.
Table 8-11 Master Subsystem Analog and EPI
µDMA ACCESS M ADDRESS
(BYTE-ALIGNED)(1)		 MASTER SUBSYSTEM
ANALOG AND EPI		 SIZE
(BYTES)		 C ADDRESS
(x16 ALIGNED)(2)		 C DMA ACCESS(2)
5000 0000 – 5000 15FF Reserved
yes 5000 1600 – 5000 161F ADC1 Result Registers 32
5000 1620 – 5000 167F Reserved
yes 5000 1680 – 5000 169F ADC2 Result Registers 32
5000 16A0 – 5FFF FFFF Reserved
yes 6000 0000 – DFFF FFFF EPI0
(External Peripheral/Memory Interface)		 2G 0030 0000 – 003F 7FFF(3)(4) yes
(1) The letter "M" refers to the Master Subsystem.
(2) The letter "C" refers to the Control Subsystem.
(3) The Control Subsystem has no direct access to EPI in silicon revision 0 devices.
(4) The Control Subsystem has less address reach to EPI memory than the Master Subsystem.
Table 8-12 Cortex-M3 Private Bus
µDMA ACCESS Cortex-M3 ADDRESS
(BYTE-ALIGNED)		 Cortex-M3 PRIVATE BUS SIZE
(BYTES)
no E000 0000 – E000 0FFF ITM (Instrumentation Trace Macrocell) 4K
no E000 1000 – E000 1FFF DWT (Data Watchpoint and Trace) 4K
no E000 2000 – E000 2FFF FPB (Flash Patch and Breakpoint) 4K
E000 3000 – E000 E007 Reserved
no E000 E008 – E000 E00F System Control Block 8
no E000 E010 – E000 E01F System Timer 16
E000 E020 – E000 E0FF Reserved
no E000 E100 – E000 E4EF Nested Vectored Interrupt Controller (NVIC) 1008
E000 E4F0 – E000 ECFF Reserved
no E000 ED00 – E000 ED3F System Control Block 64
E000 ED40 – E000 ED8F Reserved
no E000 ED90 – E000 EDB8 Memory Protection Unit 41
E000 EDB9 – E000 EEFF Reserved
no E000 EF00 – E000 EF03 Nested Vectored Interrupt Controller 4
E000 EF04 – FFFF FFFF Reserved
Note:

MPU is not available on silicon revision 0 devices.