JAJSJA4L June   2011  – February 2021 F28M35E20B , F28M35H22C , F28M35H52C , F28M35H52C-Q1 , F28M35M22C , F28M35M52C

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1. 3.1 機能ブロック図
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
      1. 6.2.1 Signal Descriptions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Automotive
    3. 7.3  ESD Ratings – Commercial
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK
      2. 7.5.2 Current Consumption at 100-MHz C28x SYSCLKOUT and 100-MHz M3SSCLK
      3. 7.5.3 Current Consumption at 75-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK
      4. 7.5.4 Current Consumption at 60-MHz C28x SYSCLKOUT and 60-MHz M3SSCLK
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics for RFP PowerPAD Package
    8. 7.8  Thermal Design Considerations
    9. 7.9  Timing and Switching Characteristics
      1. 7.9.1 Power Sequencing
        1. 7.9.1.1 Reset ( XRS) Timing Requirements
        2. 7.9.1.2 Reset ( XRS) Switching Characteristics
        3. 7.9.1.3 Power Management and Supervisory Circuit Solutions
      2. 7.9.2 Clock Specifications
        1. 7.9.2.1 Changing the Frequency of the Main PLL
        2. 7.9.2.2 Input Clock Frequency and Timing Requirements, PLL Lock Times
          1. 7.9.2.2.1 Input Clock Frequency
          2. 7.9.2.2.2 Crystal Oscillator Electrical Characteristics
          3. 7.9.2.2.3 X1 Timing Requirements - PLL Enabled (1)
          4. 7.9.2.2.4 X1 Timing Requirements - PLL Disabled
          5. 7.9.2.2.5 XCLKIN Timing Requirements - PLL Enabled
          6. 7.9.2.2.6 XCLKIN Timing Requirements - PLL Disabled
          7. 7.9.2.2.7 PLL Lock Times
        3. 7.9.2.3 Output Clock Frequency and Switching Characteristics
          1. 7.9.2.3.1 Output Clock Frequency
          2. 7.9.2.3.2 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (1)
        4. 7.9.2.4 Internal Clock Frequencies
          1. 7.9.2.4.1 Internal Clock Frequencies (150-MHz Devices)
      3. 7.9.3 Timing Parameter Symbology
        1. 7.9.3.1 General Notes on Timing Parameters
        2. 7.9.3.2 Test Load Circuit
      4. 7.9.4 Flash Timing – Master Subsystem
        1. 7.9.4.1 Master Subsystem – Flash/OTP Endurance
        2. 7.9.4.2 Master Subsystem – Flash Parameters
        3. 7.9.4.3 Master Subsystem – Flash/OTP Access Timing
        4. 7.9.4.4 Master Subsystem – Flash Data Retention Duration
        5. 7.9.4.5 Master Subsystem – Minimum Required Flash/OTP Wait States at Different Frequencies
      5. 7.9.5 Flash Timing – Control Subsystem
        1. 7.9.5.1 Control Subsystem – Flash/OTP Endurance
        2. 7.9.5.2 Control Subsystem – Flash Parameters
        3. 7.9.5.3 Control Subsystem – Flash/OTP Access Timing
        4. 7.9.5.4 Control Subsystem – Flash Data Retention Duration
      6. 7.9.6 GPIO Electrical Data and Timing
        1. 7.9.6.1 GPIO - Output Timing
          1. 7.9.6.1.1 General-Purpose Output Switching Characteristics
        2. 7.9.6.2 GPIO - Input Timing
          1. 7.9.6.2.1 General-Purpose Input Timing Requirements
        3. 7.9.6.3 Sampling Window Width for Input Signals
        4. 7.9.6.4 Low-Power Mode Wakeup Timing
          1. 7.9.6.4.1 IDLE Mode Timing Requirements
          2. 7.9.6.4.2 IDLE Mode Switching Characteristics
          3. 7.9.6.4.3 IDLE Entry and Exit Timing Diagram
          4. 7.9.6.4.4 STANDBY Mode Timing Requirements
          5. 7.9.6.4.5 STANDBY Mode Switching Characteristics
          6. 7.9.6.4.6 STANDBY Entry and Exit Timing Diagram
          7. 7.9.6.4.7 HALT Mode Timing Requirements
          8. 7.9.6.4.8 HALT Mode Switching Characteristics
          9. 7.9.6.4.9 HALT Entry and Exit Timing Diagram
      7. 7.9.7 External Interrupt Electrical Data and Timing
        1. 7.9.7.1 External Interrupt Timing Requirements
        2. 7.9.7.2 External Interrupt Switching Characteristics
        3. 7.9.7.3 External Interrupt Timing Diagram
    10. 7.10 Analog and Shared Peripherals
      1. 7.10.1 Analog-to-Digital Converter
        1. 7.10.1.1 Sample Mode
        2. 7.10.1.2 Start-of-Conversion Triggers
        3. 7.10.1.3 Analog Inputs
        4. 7.10.1.4 ADC Result Registers and EOC Interrupts
        5. 7.10.1.5 ADC Electrical Data and Timing
          1. 7.10.1.5.1 ADC Electrical Characteristics
          2. 7.10.1.5.2 External ADC Start-of-Conversion Switching Characteristics
          3. 7.10.1.5.3 ADCSOCAO or ADCSOCBO Timing Diagram
      2. 7.10.2 Comparator + DAC Units
        1. 7.10.2.1 On-Chip Comparator and DAC Electrical Data and Timing
          1. 7.10.2.1.1 Electrical Characteristics of the Comparator/DAC
      3. 7.10.3 Interprocessor Communications
      4. 7.10.4 External Peripheral Interface
        1. 7.10.4.1 EPI General-Purpose Mode
        2. 7.10.4.2 EPI SDRAM Mode
        3. 7.10.4.3 EPI Host Bus Mode
          1. 7.10.4.3.1 EPI 8-Bit Host Bus (HB-8) Mode
            1. 7.10.4.3.1.1 HB-8 Muxed Address/Data Mode
            2. 7.10.4.3.1.2 HB-8 Non-Muxed Address/Data Mode
            3. 7.10.4.3.1.3 HB-8 FIFO Mode
          2. 7.10.4.3.2 EPI 16-Bit Host Bus (HB-16) Mode
            1. 7.10.4.3.2.1 HB-16 Muxed Address/Data Mode
            2. 7.10.4.3.2.2 HB-16 Non-Muxed Address/Data Mode
            3. 7.10.4.3.2.3 HB-16 FIFO Mode
        4. 7.10.4.4 EPI Electrical Data and Timing
          1. 7.10.4.4.1 EPI SDRAM Interface Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (see Figure 1-1 , Figure 1-1 , and Figure 1-1 )
          2. 7.10.4.4.2 EPI SDRAM Timing Diagrams
          3. 7.10.4.4.3 EPI Host-Bus 8 and Host-Bus 16 Interface Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (see Figure 1-1 , Figure 1-1 , Figure 1-1 , and Figure 1-1 )
          4. 7.10.4.4.4 EPI Host-Bus 8 and Host-Bus 16 Interface Timing Requirements (1) (see Figure 1-1 and Figure 1-1 )
          5. 7.10.4.4.5 EPI Host-Bus 8/16 Mode Timing Diagrams
          6. 7.10.4.4.6 EPI General-Purpose Interface Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (see Figure 1-1 )
          7. 7.10.4.4.7 EPI General-Purpose Interface Timing Requirements (see Figure 1-1 and Figure 1-1 )
          8. 7.10.4.4.8 EPI General-Purpose Interface Timing Diagrams
    11. 7.11 Master Subsystem Peripherals
      1. 7.11.1 Synchronous Serial Interface
        1. 7.11.1.1 Bit Rate Generation
        2. 7.11.1.2 Transmit FIFO
        3. 7.11.1.3 Receive FIFO
        4. 7.11.1.4 Interrupts
        5. 7.11.1.5 Frame Formats
      2. 7.11.2 Universal Asynchronous Receiver/Transmitter
        1. 7.11.2.1 Baud-Rate Generation
        2. 7.11.2.2 Transmit and Receive Logic
        3. 7.11.2.3 Data Transmission and Reception
        4. 7.11.2.4 Interrupts
      3. 7.11.3 Cortex-M3 Inter-Integrated Circuit
        1. 7.11.3.1 Functional Overview
        2. 7.11.3.2 Available Speed Modes
        3. 7.11.3.3 I2C Electrical Data and Timing
          1. 7.11.3.3.1 I2C Timing
      4. 7.11.4 Cortex-M3 Controller Area Network
        1. 7.11.4.1 Functional Overview
      5. 7.11.5 Cortex-M3 Universal Serial Bus Controller
        1. 7.11.5.1 Functional Description
      6. 7.11.6 Cortex-M3 Ethernet Media Access Controller
        1. 7.11.6.1 Functional Overview
        2. 7.11.6.2 MII Signals
        3. 7.11.6.3 EMAC Electrical Data and Timing
          1. 7.11.6.3.1 Timing Requirements for MIITXCK (see Figure 1-1 )
          2. 7.11.6.3.2 MIITXCK Timing Diagrams
          3. 7.11.6.3.3 Timing Requirements for MIIRXCK (see Figure 1-1 )
          4. 7.11.6.3.4 MIIRXCK Timing Diagram
          5. 7.11.6.3.5 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for EMAC MII Transmit (see Figure 1-1 )
          6. 7.11.6.3.6 EMAC MII Transmit Timing Diagram
          7. 7.11.6.3.7 Timing Requirements for EMAC MII Receive (see Figure 1-1 )
          8. 7.11.6.3.8 EMAC MII Receive Timing Diagram
        4. 7.11.6.4 MDIO Electrical Data and Timing
          1. 7.11.6.4.1 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for MDIO_CK (see Figure 1-1 )
          2. 7.11.6.4.2 MDIO_CK Timing Diagram
          3. 7.11.6.4.3 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for MDIO as Output (see Figure 1-1 )
          4. 7.11.6.4.4 MDIO as Output Timing Diagram
          5. 7.11.6.4.5 Timing Requirements for MDIO as Input (see Figure 1-1 )
          6. 7.11.6.4.6 MDIO as Input Timing Diagram
    12. 7.12 Control Subsystem Peripherals
      1. 7.12.1 High-Resolution PWM and Enhanced PWM Modules
        1. 7.12.1.1 HRPWM Electrical Data and Timing
          1. 7.12.1.1.1 High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz)
        2. 7.12.1.2 ePWM Electrical Data and Timing
          1. 7.12.1.2.1 ePWM Timing Requirements
          2. 7.12.1.2.2 ePWM Switching Characteristics
          3. 7.12.1.2.3 Trip-Zone Input Timing
            1. 7.12.1.2.3.1 Trip-Zone Input Timing Requirements
      2. 7.12.2 Enhanced Capture Module
        1. 7.12.2.1 eCAP Electrical Data and Timing
          1. 7.12.2.1.1 eCAP Timing Requirement
          2. 7.12.2.1.2 eCAP Switching Characteristics
      3. 7.12.3 Enhanced Quadrature Encoder Pulse Module
        1. 7.12.3.1 eQEP Electrical Data and Timing
          1. 7.12.3.1.1 eQEP Timing Requirements
          2. 7.12.3.1.2 eQEP Switching Characteristics
      4. 7.12.4 C28x Inter-Integrated Circuit Module
        1. 7.12.4.1 Functional Overview
        2. 7.12.4.2 Clock Generation
        3. 7.12.4.3 I2C Electrical Data and Timing
          1. 7.12.4.3.1 I2C Timing
      5. 7.12.5 C28x Serial Communications Interface
        1. 7.12.5.1 Architecture
        2. 7.12.5.2 Multiprocessor and Asynchronous Communication Modes
      6. 7.12.6 C28x Serial Peripheral Interface
        1. 7.12.6.1 Functional Overview
        2. 7.12.6.2 SPI Electrical Data and Timing
          1. 7.12.6.2.1 Master Mode Timing
            1. 7.12.6.2.1.1 SPI Master Mode External Timing (Clock Phase = 0)
            2. 7.12.6.2.1.2 SPI Master Mode External Timing (Clock Phase = 1)
          2. 7.12.6.2.2 Slave Mode Timing
            1. 7.12.6.2.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
            2. 7.12.6.2.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
      7. 7.12.7 C28x Multichannel Buffered Serial Port
        1. 7.12.7.1 McBSP Electrical Data and Timing
          1. 7.12.7.1.1 McBSP Transmit and Receive Timing
            1. 7.12.7.1.1.1 McBSP Timing Requirements
            2. 7.12.7.1.1.2 McBSP Switching Characteristics
            3. 7.12.7.1.1.3 McBSP Timing Diagrams
          2. 7.12.7.1.2 McBSP as SPI Master or Slave Timing
            1. 7.12.7.1.2.1  McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. 7.12.7.1.2.2  McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 10b, CLKXP = 0)
            3. 7.12.7.1.2.3  McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 Timing Diagram
            4. 7.12.7.1.2.4  McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            5. 7.12.7.1.2.5  McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 11b, CLKXP = 0)
            6. 7.12.7.1.2.6  McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 Timing Diagram
            7. 7.12.7.1.2.7  McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            8. 7.12.7.1.2.8  McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 10b, CLKXP = 1)
            9. 7.12.7.1.2.9  McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 Timing Diagram
            10. 7.12.7.1.2.10 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            11. 7.12.7.1.2.11 McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 11b, CLKXP = 1)
            12. 7.12.7.1.2.12 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 Timing Diagram
  8. 8 Detailed Description
    1. 8.1  Memory Maps
      1. 8.1.1 Control Subsystem Memory Map
      2. 8.1.2 Master Subsystem Memory Map
    2. 8.2  Identification
    3. 8.3  Master Subsystem
      1. 8.3.1 Cortex-M3 CPU
      2. 8.3.2 Cortex-M3 DMA and NVIC
      3. 8.3.3 Cortex-M3 Interrupts
      4. 8.3.4 Cortex-M3 Vector Table
      5. 8.3.5 Cortex-M3 Local Peripherals
      6. 8.3.6 Cortex-M3 Local Memory
      7. 8.3.7 Cortex-M3 Accessing Shared Resources and Analog Peripherals
    4. 8.4  Control Subsystem
      1. 8.4.1 C28x CPU/FPU/VCU
      2. 8.4.2 C28x Core Hardware Built-In Self-Test
      3. 8.4.3 C28x Peripheral Interrupt Expansion
      4. 8.4.4 C28x Direct Memory Access
      5. 8.4.5 C28x Local Peripherals
      6. 8.4.6 C28x Local Memory
      7. 8.4.7 C28x Accessing Shared Resources and Analog Peripherals
    5. 8.5  Analog Subsystem
      1. 8.5.1 ADC1
      2. 8.5.2 ADC2
      3. 8.5.3 Analog Comparator + DAC
      4. 8.5.4 Analog Common Interface Bus
    6. 8.6  Master Subsystem NMIs
    7. 8.7  Control Subsystem NMIs
    8. 8.8  Resets
      1. 8.8.1 Cortex-M3 Resets
      2. 8.8.2 C28x Resets
      3. 8.8.3 Analog Subsystem and Shared Resources Resets
      4. 8.8.4 Device Boot Sequence
    9. 8.9  Internal Voltage Regulation and Power-On-Reset Functionality
      1. 8.9.1 Analog Subsystem: Internal 1.8-V VREG
      2. 8.9.2 Digital Subsystem: Internal 1.2-V VREG
      3. 8.9.3 Analog and Digital Subsystems: Power-On-Reset Functionality
      4. 8.9.4 Connecting ARS and XRS Pins
    10. 8.10 Input Clocks and PLLs
      1. 8.10.1 Internal Oscillator (Zero-Pin)
      2. 8.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC)
      3. 8.10.3 External Oscillators (Pins X1 and XCLKIN)
      4. 8.10.4 Main PLL
      5. 8.10.5 USB PLL
    11. 8.11 Master Subsystem Clocking
      1. 8.11.1 Cortex-M3 Run Mode
      2. 8.11.2 Cortex-M3 Sleep Mode
      3. 8.11.3 Cortex-M3 Deep Sleep Mode
    12. 8.12 Control Subsystem Clocking
      1. 8.12.1 C28x Normal Mode
      2. 8.12.2 C28x IDLE Mode
      3. 8.12.3 C28x STANDBY Mode
    13. 8.13 Analog Subsystem Clocking
    14. 8.14 Shared Resources Clocking
    15. 8.15 Loss of Input Clock (NMI Watchdog Function)
    16. 8.16 GPIOs and Other Pins
      1. 8.16.1 GPIO_MUX1
      2. 8.16.2 GPIO_MUX2
      3. 8.16.3 AIO_MUX1
      4. 8.16.4 AIO_MUX2
    17. 8.17 Emulation/JTAG
    18. 8.18 Code Security Module
      1. 8.18.1 Functional Description
    19. 8.19 µCRC Module
      1. 8.19.1 Functional Description
      2. 8.19.2 CRC Polynomials
      3. 8.19.3 CRC Calculation Procedure
      4. 8.19.4 CRC Calculation for Data Stored In Secure Memory
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Device and Development Support Tool Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Trademarks
    5. 10.5 サポート・リソース
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.3 Cortex-M3 Interrupts

Table 8-14 shows all interrupt assignments for the Cortex-M3 processor. Most interrupts (16–107) are associated with interrupt requests from Cortex-M3 peripherals. The first 15 interrupts (1–15) are processor exceptions generated by the Cortex-M3 core itself. These processor exceptions are detailed in Table 8-15.

Table 8-14 Interrupts from NVIC to Cortex-M3
INTERRUPT NUMBER
(BIT IN INTERRUPT REGISTERS)		 VECTOR NUMBER VECTOR ADDRESS OR OFFSET DESCRIPTION
– 0–15 0x0000.0000–0x0000.003C Processor exceptions
0 16 0x0000.0040 GPIO Port A
1 17 0x0000.0044 GPIO Port B
2 18 0x0000.0048 GPIO Port C
3 19 0x0000.004C GPIO Port D
4 20 0x0000.0050 GPIO Port E
5 21 0x0000.0054 UART0
6 22 0x0000.0058 UART1
7 23 0x0000.005C SSI0
8 24 0x0000.0060 I2C0
9–17 25–33 – Reserved
18 34 0x0000.0088 Watchdog Timers 0 and 1
19 35 0x0000.008C Timer 0A
20 36 0x0000.0090 Timer 0B
21 37 0x0000.0094 Timer 1A
22 38 0x0000.0098 Timer 1B
23 39 0x0000.009C Timer 2A
24 40 0x0000.00A0 Timer 2B
25–27 41–43 – Reserved
28 44 0x0000.00B0 System Control
29 45 0x0000.00B4 Reserved
30 46 0x0000.00B8 GPIO Port F
31 47 0x0000.00BC GPIO Port G
32 48 0x0000.00C0 GPIO Port H
33 49 0x0000.00C4 UART2
34 50 0x0000.00C8 SSI1
35 51 0x0000.00CC Timer 3A
36 52 0x0000.00D0 Timer 3B
37 53 0x0000.00D4 I2C1
38–41 54–57 – Reserved
42 58 0x0000.00E8 Ethernet Controller
44 60 0x0000.00F0 USB
45 61 – Reserved
46 62 0x0000.00F8 µDMA Software
47 63 0x0000.00FC µDMA Error
48–52 64–68 – Reserved
53 69 0x0000.0114 EPI
54 70 0x0000.0118 GPIO Port J
55–56 71–72 – Reserved
57 73 0x0000.0124 SSI 2
58 74 0x0000.0128 SSI 3
59 75 0x0000.012C UART3
60 76 0x0000.0130 UART4
61–63 77–79 – Reserved
64 80 0x0000.0140 CAN0 INT0
65 81 0x0000.0144 CAN0 INT1
66 82 0x0000.0148 CAN1 INT0
67 83 0x0000.014C CAN1 INT1
68–71 84–87 – Reserved
72 88 0x0000.0160 ADCINT1
73 89 0x0000.0164 ADCINT2
74 90 0x0000.0168 ADCINT3
75 91 0x0000.016C ADCINT4
76 92 0x0000.0170 ADCINT5
77 93 0x0000.0174 ADCINT6
78 94 0x0000.0178 ADCINT7
79 95 0x0000.017C ADCINT8
80 96 0x0000.0180 CTOMIPC1
81 97 0x0000.0184 CTOMIPC2
82 98 0x0000.0188 CTOMIPC3
83 99 0x0000.018C CTOMIPC4
84–87 100–103 – Reserved
88 104 0x0000.01A0 RAM Single Error
89 105 0x0000.01A4 System / USB PLL Out of Lock
90 106 0x0000.01A8 M3 Flash Single Error
91 107 0x0000.01AC Reserved
92–133 108–149 – Reserved
Table 8-15 Exceptions from Cortex-M3 Core to NVIC
EXCEPTION TYPE PRIORITY(1) VECTOR NUMBER VECTOR ADDRESS OR OFFSET(2) ACTIVATION
– – 0 0x0000.0000 Stack top is loaded from the first entry of the vector table on reset.
Reset –3 (highest) 1 0x0000.0004 Asynchronous
Nonmaskable Interrupt (NMI) –2 2 0x0000.0008 Asynchronous
On Concerto devices activated by clock fail condition, C28 PIE error, external M3GPIO NMI input signal, and C28 NMI WD time-out reset.
Hard Fault –1 3 0x0000.000C –
Memory Management programmable(3) 4 0x0000.0010 Synchronous
Bus Fault programmable(3) 5 0x0000.0014 Synchronous when precise and asynchronous when imprecise.
On Concerto devices activated by memory access errors and RAM and flash uncorrectable data errors.
Usage Fault programmable(3) 6 0x0000.0018 Synchronous
– – 7–10 – Reserved
SVCall programmable(3) 11 0x0000.002C Synchronous
Debug Monitor programmable(3) 12 0x0000.0030 Synchronous
– – 13 – Reserved
PendSV programmable(3) 14 0x0000.0038 Asynchronous
SysTick programmable(3) 15 0x0000.003C Asynchronous
Interrupts programmable (4) 16 and above 0x0000.0040 and above Asynchronous
(1) 0 is the default priority for all the programmable priorities
(2) See the "Vector Table" subsection of the "Exception Model" section in the Cortex-M3 Processor chapter of the Concerto F28M35x Technical Reference Manual.
(3) See SYSPRI1 in the Cortex-M3 Peripherals chapter of the Concerto F28M35x Technical Reference Manual.
(4) See PRIn registers in the Cortex-M3 Peripherals chapter of the Concerto F28M35x Technical Reference Manual.