JAJSJA4L June   2011  – February 2021 F28M35E20B , F28M35H22C , F28M35H52C , F28M35H52C-Q1 , F28M35M22C , F28M35M52C

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1. 3.1 機能ブロック図
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
      1. 6.2.1 Signal Descriptions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Automotive
    3. 7.3  ESD Ratings – Commercial
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK
      2. 7.5.2 Current Consumption at 100-MHz C28x SYSCLKOUT and 100-MHz M3SSCLK
      3. 7.5.3 Current Consumption at 75-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK
      4. 7.5.4 Current Consumption at 60-MHz C28x SYSCLKOUT and 60-MHz M3SSCLK
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics for RFP PowerPAD Package
    8. 7.8  Thermal Design Considerations
    9. 7.9  Timing and Switching Characteristics
      1. 7.9.1 Power Sequencing
        1. 7.9.1.1 Reset ( XRS) Timing Requirements
        2. 7.9.1.2 Reset ( XRS) Switching Characteristics
        3. 7.9.1.3 Power Management and Supervisory Circuit Solutions
      2. 7.9.2 Clock Specifications
        1. 7.9.2.1 Changing the Frequency of the Main PLL
        2. 7.9.2.2 Input Clock Frequency and Timing Requirements, PLL Lock Times
          1. 7.9.2.2.1 Input Clock Frequency
          2. 7.9.2.2.2 Crystal Oscillator Electrical Characteristics
          3. 7.9.2.2.3 X1 Timing Requirements - PLL Enabled (1)
          4. 7.9.2.2.4 X1 Timing Requirements - PLL Disabled
          5. 7.9.2.2.5 XCLKIN Timing Requirements - PLL Enabled
          6. 7.9.2.2.6 XCLKIN Timing Requirements - PLL Disabled
          7. 7.9.2.2.7 PLL Lock Times
        3. 7.9.2.3 Output Clock Frequency and Switching Characteristics
          1. 7.9.2.3.1 Output Clock Frequency
          2. 7.9.2.3.2 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (1)
        4. 7.9.2.4 Internal Clock Frequencies
          1. 7.9.2.4.1 Internal Clock Frequencies (150-MHz Devices)
      3. 7.9.3 Timing Parameter Symbology
        1. 7.9.3.1 General Notes on Timing Parameters
        2. 7.9.3.2 Test Load Circuit
      4. 7.9.4 Flash Timing – Master Subsystem
        1. 7.9.4.1 Master Subsystem – Flash/OTP Endurance
        2. 7.9.4.2 Master Subsystem – Flash Parameters
        3. 7.9.4.3 Master Subsystem – Flash/OTP Access Timing
        4. 7.9.4.4 Master Subsystem – Flash Data Retention Duration
        5. 7.9.4.5 Master Subsystem – Minimum Required Flash/OTP Wait States at Different Frequencies
      5. 7.9.5 Flash Timing – Control Subsystem
        1. 7.9.5.1 Control Subsystem – Flash/OTP Endurance
        2. 7.9.5.2 Control Subsystem – Flash Parameters
        3. 7.9.5.3 Control Subsystem – Flash/OTP Access Timing
        4. 7.9.5.4 Control Subsystem – Flash Data Retention Duration
      6. 7.9.6 GPIO Electrical Data and Timing
        1. 7.9.6.1 GPIO - Output Timing
          1. 7.9.6.1.1 General-Purpose Output Switching Characteristics
        2. 7.9.6.2 GPIO - Input Timing
          1. 7.9.6.2.1 General-Purpose Input Timing Requirements
        3. 7.9.6.3 Sampling Window Width for Input Signals
        4. 7.9.6.4 Low-Power Mode Wakeup Timing
          1. 7.9.6.4.1 IDLE Mode Timing Requirements
          2. 7.9.6.4.2 IDLE Mode Switching Characteristics
          3. 7.9.6.4.3 IDLE Entry and Exit Timing Diagram
          4. 7.9.6.4.4 STANDBY Mode Timing Requirements
          5. 7.9.6.4.5 STANDBY Mode Switching Characteristics
          6. 7.9.6.4.6 STANDBY Entry and Exit Timing Diagram
          7. 7.9.6.4.7 HALT Mode Timing Requirements
          8. 7.9.6.4.8 HALT Mode Switching Characteristics
          9. 7.9.6.4.9 HALT Entry and Exit Timing Diagram
      7. 7.9.7 External Interrupt Electrical Data and Timing
        1. 7.9.7.1 External Interrupt Timing Requirements
        2. 7.9.7.2 External Interrupt Switching Characteristics
        3. 7.9.7.3 External Interrupt Timing Diagram
    10. 7.10 Analog and Shared Peripherals
      1. 7.10.1 Analog-to-Digital Converter
        1. 7.10.1.1 Sample Mode
        2. 7.10.1.2 Start-of-Conversion Triggers
        3. 7.10.1.3 Analog Inputs
        4. 7.10.1.4 ADC Result Registers and EOC Interrupts
        5. 7.10.1.5 ADC Electrical Data and Timing
          1. 7.10.1.5.1 ADC Electrical Characteristics
          2. 7.10.1.5.2 External ADC Start-of-Conversion Switching Characteristics
          3. 7.10.1.5.3 ADCSOCAO or ADCSOCBO Timing Diagram
      2. 7.10.2 Comparator + DAC Units
        1. 7.10.2.1 On-Chip Comparator and DAC Electrical Data and Timing
          1. 7.10.2.1.1 Electrical Characteristics of the Comparator/DAC
      3. 7.10.3 Interprocessor Communications
      4. 7.10.4 External Peripheral Interface
        1. 7.10.4.1 EPI General-Purpose Mode
        2. 7.10.4.2 EPI SDRAM Mode
        3. 7.10.4.3 EPI Host Bus Mode
          1. 7.10.4.3.1 EPI 8-Bit Host Bus (HB-8) Mode
            1. 7.10.4.3.1.1 HB-8 Muxed Address/Data Mode
            2. 7.10.4.3.1.2 HB-8 Non-Muxed Address/Data Mode
            3. 7.10.4.3.1.3 HB-8 FIFO Mode
          2. 7.10.4.3.2 EPI 16-Bit Host Bus (HB-16) Mode
            1. 7.10.4.3.2.1 HB-16 Muxed Address/Data Mode
            2. 7.10.4.3.2.2 HB-16 Non-Muxed Address/Data Mode
            3. 7.10.4.3.2.3 HB-16 FIFO Mode
        4. 7.10.4.4 EPI Electrical Data and Timing
          1. 7.10.4.4.1 EPI SDRAM Interface Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (see Figure 1-1 , Figure 1-1 , and Figure 1-1 )
          2. 7.10.4.4.2 EPI SDRAM Timing Diagrams
          3. 7.10.4.4.3 EPI Host-Bus 8 and Host-Bus 16 Interface Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (see Figure 1-1 , Figure 1-1 , Figure 1-1 , and Figure 1-1 )
          4. 7.10.4.4.4 EPI Host-Bus 8 and Host-Bus 16 Interface Timing Requirements (1) (see Figure 1-1 and Figure 1-1 )
          5. 7.10.4.4.5 EPI Host-Bus 8/16 Mode Timing Diagrams
          6. 7.10.4.4.6 EPI General-Purpose Interface Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (see Figure 1-1 )
          7. 7.10.4.4.7 EPI General-Purpose Interface Timing Requirements (see Figure 1-1 and Figure 1-1 )
          8. 7.10.4.4.8 EPI General-Purpose Interface Timing Diagrams
    11. 7.11 Master Subsystem Peripherals
      1. 7.11.1 Synchronous Serial Interface
        1. 7.11.1.1 Bit Rate Generation
        2. 7.11.1.2 Transmit FIFO
        3. 7.11.1.3 Receive FIFO
        4. 7.11.1.4 Interrupts
        5. 7.11.1.5 Frame Formats
      2. 7.11.2 Universal Asynchronous Receiver/Transmitter
        1. 7.11.2.1 Baud-Rate Generation
        2. 7.11.2.2 Transmit and Receive Logic
        3. 7.11.2.3 Data Transmission and Reception
        4. 7.11.2.4 Interrupts
      3. 7.11.3 Cortex-M3 Inter-Integrated Circuit
        1. 7.11.3.1 Functional Overview
        2. 7.11.3.2 Available Speed Modes
        3. 7.11.3.3 I2C Electrical Data and Timing
          1. 7.11.3.3.1 I2C Timing
      4. 7.11.4 Cortex-M3 Controller Area Network
        1. 7.11.4.1 Functional Overview
      5. 7.11.5 Cortex-M3 Universal Serial Bus Controller
        1. 7.11.5.1 Functional Description
      6. 7.11.6 Cortex-M3 Ethernet Media Access Controller
        1. 7.11.6.1 Functional Overview
        2. 7.11.6.2 MII Signals
        3. 7.11.6.3 EMAC Electrical Data and Timing
          1. 7.11.6.3.1 Timing Requirements for MIITXCK (see Figure 1-1 )
          2. 7.11.6.3.2 MIITXCK Timing Diagrams
          3. 7.11.6.3.3 Timing Requirements for MIIRXCK (see Figure 1-1 )
          4. 7.11.6.3.4 MIIRXCK Timing Diagram
          5. 7.11.6.3.5 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for EMAC MII Transmit (see Figure 1-1 )
          6. 7.11.6.3.6 EMAC MII Transmit Timing Diagram
          7. 7.11.6.3.7 Timing Requirements for EMAC MII Receive (see Figure 1-1 )
          8. 7.11.6.3.8 EMAC MII Receive Timing Diagram
        4. 7.11.6.4 MDIO Electrical Data and Timing
          1. 7.11.6.4.1 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for MDIO_CK (see Figure 1-1 )
          2. 7.11.6.4.2 MDIO_CK Timing Diagram
          3. 7.11.6.4.3 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for MDIO as Output (see Figure 1-1 )
          4. 7.11.6.4.4 MDIO as Output Timing Diagram
          5. 7.11.6.4.5 Timing Requirements for MDIO as Input (see Figure 1-1 )
          6. 7.11.6.4.6 MDIO as Input Timing Diagram
    12. 7.12 Control Subsystem Peripherals
      1. 7.12.1 High-Resolution PWM and Enhanced PWM Modules
        1. 7.12.1.1 HRPWM Electrical Data and Timing
          1. 7.12.1.1.1 High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz)
        2. 7.12.1.2 ePWM Electrical Data and Timing
          1. 7.12.1.2.1 ePWM Timing Requirements
          2. 7.12.1.2.2 ePWM Switching Characteristics
          3. 7.12.1.2.3 Trip-Zone Input Timing
            1. 7.12.1.2.3.1 Trip-Zone Input Timing Requirements
      2. 7.12.2 Enhanced Capture Module
        1. 7.12.2.1 eCAP Electrical Data and Timing
          1. 7.12.2.1.1 eCAP Timing Requirement
          2. 7.12.2.1.2 eCAP Switching Characteristics
      3. 7.12.3 Enhanced Quadrature Encoder Pulse Module
        1. 7.12.3.1 eQEP Electrical Data and Timing
          1. 7.12.3.1.1 eQEP Timing Requirements
          2. 7.12.3.1.2 eQEP Switching Characteristics
      4. 7.12.4 C28x Inter-Integrated Circuit Module
        1. 7.12.4.1 Functional Overview
        2. 7.12.4.2 Clock Generation
        3. 7.12.4.3 I2C Electrical Data and Timing
          1. 7.12.4.3.1 I2C Timing
      5. 7.12.5 C28x Serial Communications Interface
        1. 7.12.5.1 Architecture
        2. 7.12.5.2 Multiprocessor and Asynchronous Communication Modes
      6. 7.12.6 C28x Serial Peripheral Interface
        1. 7.12.6.1 Functional Overview
        2. 7.12.6.2 SPI Electrical Data and Timing
          1. 7.12.6.2.1 Master Mode Timing
            1. 7.12.6.2.1.1 SPI Master Mode External Timing (Clock Phase = 0)
            2. 7.12.6.2.1.2 SPI Master Mode External Timing (Clock Phase = 1)
          2. 7.12.6.2.2 Slave Mode Timing
            1. 7.12.6.2.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
            2. 7.12.6.2.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
      7. 7.12.7 C28x Multichannel Buffered Serial Port
        1. 7.12.7.1 McBSP Electrical Data and Timing
          1. 7.12.7.1.1 McBSP Transmit and Receive Timing
            1. 7.12.7.1.1.1 McBSP Timing Requirements
            2. 7.12.7.1.1.2 McBSP Switching Characteristics
            3. 7.12.7.1.1.3 McBSP Timing Diagrams
          2. 7.12.7.1.2 McBSP as SPI Master or Slave Timing
            1. 7.12.7.1.2.1  McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. 7.12.7.1.2.2  McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 10b, CLKXP = 0)
            3. 7.12.7.1.2.3  McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 Timing Diagram
            4. 7.12.7.1.2.4  McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            5. 7.12.7.1.2.5  McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 11b, CLKXP = 0)
            6. 7.12.7.1.2.6  McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 Timing Diagram
            7. 7.12.7.1.2.7  McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            8. 7.12.7.1.2.8  McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 10b, CLKXP = 1)
            9. 7.12.7.1.2.9  McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 Timing Diagram
            10. 7.12.7.1.2.10 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            11. 7.12.7.1.2.11 McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 11b, CLKXP = 1)
            12. 7.12.7.1.2.12 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 Timing Diagram
  8. 8 Detailed Description
    1. 8.1  Memory Maps
      1. 8.1.1 Control Subsystem Memory Map
      2. 8.1.2 Master Subsystem Memory Map
    2. 8.2  Identification
    3. 8.3  Master Subsystem
      1. 8.3.1 Cortex-M3 CPU
      2. 8.3.2 Cortex-M3 DMA and NVIC
      3. 8.3.3 Cortex-M3 Interrupts
      4. 8.3.4 Cortex-M3 Vector Table
      5. 8.3.5 Cortex-M3 Local Peripherals
      6. 8.3.6 Cortex-M3 Local Memory
      7. 8.3.7 Cortex-M3 Accessing Shared Resources and Analog Peripherals
    4. 8.4  Control Subsystem
      1. 8.4.1 C28x CPU/FPU/VCU
      2. 8.4.2 C28x Core Hardware Built-In Self-Test
      3. 8.4.3 C28x Peripheral Interrupt Expansion
      4. 8.4.4 C28x Direct Memory Access
      5. 8.4.5 C28x Local Peripherals
      6. 8.4.6 C28x Local Memory
      7. 8.4.7 C28x Accessing Shared Resources and Analog Peripherals
    5. 8.5  Analog Subsystem
      1. 8.5.1 ADC1
      2. 8.5.2 ADC2
      3. 8.5.3 Analog Comparator + DAC
      4. 8.5.4 Analog Common Interface Bus
    6. 8.6  Master Subsystem NMIs
    7. 8.7  Control Subsystem NMIs
    8. 8.8  Resets
      1. 8.8.1 Cortex-M3 Resets
      2. 8.8.2 C28x Resets
      3. 8.8.3 Analog Subsystem and Shared Resources Resets
      4. 8.8.4 Device Boot Sequence
    9. 8.9  Internal Voltage Regulation and Power-On-Reset Functionality
      1. 8.9.1 Analog Subsystem: Internal 1.8-V VREG
      2. 8.9.2 Digital Subsystem: Internal 1.2-V VREG
      3. 8.9.3 Analog and Digital Subsystems: Power-On-Reset Functionality
      4. 8.9.4 Connecting ARS and XRS Pins
    10. 8.10 Input Clocks and PLLs
      1. 8.10.1 Internal Oscillator (Zero-Pin)
      2. 8.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC)
      3. 8.10.3 External Oscillators (Pins X1 and XCLKIN)
      4. 8.10.4 Main PLL
      5. 8.10.5 USB PLL
    11. 8.11 Master Subsystem Clocking
      1. 8.11.1 Cortex-M3 Run Mode
      2. 8.11.2 Cortex-M3 Sleep Mode
      3. 8.11.3 Cortex-M3 Deep Sleep Mode
    12. 8.12 Control Subsystem Clocking
      1. 8.12.1 C28x Normal Mode
      2. 8.12.2 C28x IDLE Mode
      3. 8.12.3 C28x STANDBY Mode
    13. 8.13 Analog Subsystem Clocking
    14. 8.14 Shared Resources Clocking
    15. 8.15 Loss of Input Clock (NMI Watchdog Function)
    16. 8.16 GPIOs and Other Pins
      1. 8.16.1 GPIO_MUX1
      2. 8.16.2 GPIO_MUX2
      3. 8.16.3 AIO_MUX1
      4. 8.16.4 AIO_MUX2
    17. 8.17 Emulation/JTAG
    18. 8.18 Code Security Module
      1. 8.18.1 Functional Description
    19. 8.19 µCRC Module
      1. 8.19.1 Functional Description
      2. 8.19.2 CRC Polynomials
      3. 8.19.3 CRC Calculation Procedure
      4. 8.19.4 CRC Calculation for Data Stored In Secure Memory
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Device and Development Support Tool Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Trademarks
    5. 10.5 サポート・リソース
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.3 C28x Peripheral Interrupt Expansion

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the F28M35x, 66 of the possible 96 interrupts are used. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of 12 interrupt lines supports up to 8 simultaneously active interrupts. Each of the 96 interrupts has its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. Eight CPU clock cycles are needed to fetch the vector and save critical CPU registers. Hence, the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled or disabled within the PIE block. See Table 8-16 for PIE interrupt assignments.

Table 8-16 PIE Peripheral Interrupts
CPU INTERRUPTS(1) PIE INTERRUPTS
INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1
INT1 C28.LPMWAKE
(C28LPM)
0x0D4E		 TINT0
(TIMER 0)
0x0D4C		 Reserved
–
0x0D4A		 XINT2
–
0x0D48		 XINT1
–
0x0D46		 Reserved
–
0x0D44		 ADCINT2
(ADC)
0x0D42		 ADCINT1
(ADC)
0x0D40
INT2 EPWM8_TZINT
(ePWM8)
0x0D5E		 EPWM7_TZINT
(ePWM7)
0x0D5C		 EPWM6_TZINT
(ePWM6)
0x0D5A		 EPWM5_TZINT
(ePWM5)
0x0D58		 EPWM4_TZINT
(ePWM4)
0x0D56		 EPWM3_TZINT
(ePWM3)
0x0D54		 EPWM2_TZINT
(ePWM2)
0x0D52		 EPWM1_TZINT
(ePWM1)
0x0D50
INT3 EPWM8_INT
(ePWM8)
0x0D6E		 EPWM7_INT
(ePWM7)
0x0D6C		 EPWM6_INT
(ePWM6)
0x0D6A		 EPWM5_INT
(ePWM5)
0x0D68		 EPWM4_INT
(ePWM4)
0x0D66		 EPWM3_INT
(ePWM3)
0x0D64		 EPWM2_INT
(ePWM2)
0x0D62		 EPWM1_INT
(ePWM1)
0x0D60
INT4 EPWM9_TZINT
(ePWM9)
0x0D7E		 Reserved
–
0x0D7C		 ECAP6_INT
(eCAP6)
0x0D7A		 ECAP5_INT
(eCAP5)
0x0D78		 ECAP4_INT
(eCAP4)
0x0D76		 ECAP3_INT
(eCAP3)
0x0D74		 ECAP2_INT
(eCAP2)
0x0D72		 ECAP1_INT
(eCAP1)
0x0D70
INT5 EPWM9_INT
(ePWM9)
0x0D8E		 Reserved
–
0x0D8C		 Reserved
–
0x0D8A		 Reserved
–
0x0D88		 Reserved
–
0x0D86		 EQEP3_INT
(eQEP3)
0x0D84		 EQEP2_INT
(eQEP2)
0x0D82		 EQEP1_INT
(eQEP1)
0x0D80
INT6 Reserved
–
0x0D9E		 Reserved
–
0x0D9C		 MXINTA
(McBSPA)
0x0D9A		 MRINTA
(McBSPA)
0x0D98		 Reserved
–
0x0D96		 Reserved
–
0x0D94		 SPITXINTA
(SPIA)
0x0D92		 SPIRXINTA
(SPIA)
0x0D90
INT7 Reserved
–
0x0DAE		 Reserved
–
0x0DAC		 DINTCH6
(C28 DMA)
0x0DAA		 DINTCH5
(C28 DMA)
0x0DA8		 DINTCH4
(C28 DMA)
0x0DA6		 DINTCH3
(C28 DMA)
0x0DA4		 DINTCH2
(C28 DMA)
0x0DA2		 DINTCH1
(C28 DMA)
0x0DA0
INT8 Reserved
–
0x0DBE		 Reserved
–
0x0DBC		 Reserved
–
0x0DBA		 Reserved
–
0x0DB8		 Reserved
–
0x0DB6		 Reserved
–
0x0DB4		 I2CINT2A
(I2CA)
0x0DB2		 I2CINT1A
(I2CA)
0x0DB0
INT9 Reserved
–
0x0DCE		 Reserved
–
0x0DCC		 Reserved
–
0x0DCA		 Reserved
–
0x0DC8		 Reserved
–
0x0DC6		 Reserved
–
0x0DC4		 SCITXINTA
(SCIA)
0x0DC2		 SCIRXINTA
(SCIA)
0x0DC0
INT10 ADCINT8
(ADC)
0x0DDE		 ADCINT7
(ADC)
0x0DDC		 ADCINT6
(ADC)
0x0DDA		 ADCINT5
(ADC)
0x0DD8		 ADCINT4
(ADC)
0x0DD6		 ADCINT3
(ADC)
0x0DD4		 ADCINT2
(ADC)
0x0DD2		 ADCINT1
(ADC)
0x0DD0
INT11 Reserved
–
0x0DEE		 Reserved
–
0x0DEC		 Reserved
–
0x0DEA		 Reserved
–
0x0DE8		 MTOCIPCINT4
(IPC)
0x0DE6 		 MTOCIPCINT3
(IPC)
0x0DE4		 MTOCIPCINT2
(IPC)
0x0DE2		 MTOCIPCINT1
(IPC)
0x0DE0
INT12 LUF
(C28FPU)
0x0DFE		 LVF
(C28FPU)
0x0DFC		 EPI_INT
(EPI)
0x0DFA		 C28RAMACCVIOL
(Memory)
0x0DF8		 C28RAMSINGERR
(Memory)
0x0DF6		 Reserved
–
0x0DF4		 C28FLSINGERR
(Memory)
0x0DF2		 XINT3
(Ext. Int. 3)
0x0DF0
(1) Out of the 96 possible interrupts, 66 interrupts are currently used. The remaining interrupts are reserved for future devices. These interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 11).