JAJSJA4L June   2011  – February 2021 F28M35E20B , F28M35H22C , F28M35H52C , F28M35H52C-Q1 , F28M35M22C , F28M35M52C

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1. 3.1 機能ブロック図
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
      1. 6.2.1 Signal Descriptions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Automotive
    3. 7.3  ESD Ratings – Commercial
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK
      2. 7.5.2 Current Consumption at 100-MHz C28x SYSCLKOUT and 100-MHz M3SSCLK
      3. 7.5.3 Current Consumption at 75-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK
      4. 7.5.4 Current Consumption at 60-MHz C28x SYSCLKOUT and 60-MHz M3SSCLK
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics for RFP PowerPAD Package
    8. 7.8  Thermal Design Considerations
    9. 7.9  Timing and Switching Characteristics
      1. 7.9.1 Power Sequencing
        1. 7.9.1.1 Reset ( XRS) Timing Requirements
        2. 7.9.1.2 Reset ( XRS) Switching Characteristics
        3. 7.9.1.3 Power Management and Supervisory Circuit Solutions
      2. 7.9.2 Clock Specifications
        1. 7.9.2.1 Changing the Frequency of the Main PLL
        2. 7.9.2.2 Input Clock Frequency and Timing Requirements, PLL Lock Times
          1. 7.9.2.2.1 Input Clock Frequency
          2. 7.9.2.2.2 Crystal Oscillator Electrical Characteristics
          3. 7.9.2.2.3 X1 Timing Requirements - PLL Enabled (1)
          4. 7.9.2.2.4 X1 Timing Requirements - PLL Disabled
          5. 7.9.2.2.5 XCLKIN Timing Requirements - PLL Enabled
          6. 7.9.2.2.6 XCLKIN Timing Requirements - PLL Disabled
          7. 7.9.2.2.7 PLL Lock Times
        3. 7.9.2.3 Output Clock Frequency and Switching Characteristics
          1. 7.9.2.3.1 Output Clock Frequency
          2. 7.9.2.3.2 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (1)
        4. 7.9.2.4 Internal Clock Frequencies
          1. 7.9.2.4.1 Internal Clock Frequencies (150-MHz Devices)
      3. 7.9.3 Timing Parameter Symbology
        1. 7.9.3.1 General Notes on Timing Parameters
        2. 7.9.3.2 Test Load Circuit
      4. 7.9.4 Flash Timing – Master Subsystem
        1. 7.9.4.1 Master Subsystem – Flash/OTP Endurance
        2. 7.9.4.2 Master Subsystem – Flash Parameters
        3. 7.9.4.3 Master Subsystem – Flash/OTP Access Timing
        4. 7.9.4.4 Master Subsystem – Flash Data Retention Duration
        5. 7.9.4.5 Master Subsystem – Minimum Required Flash/OTP Wait States at Different Frequencies
      5. 7.9.5 Flash Timing – Control Subsystem
        1. 7.9.5.1 Control Subsystem – Flash/OTP Endurance
        2. 7.9.5.2 Control Subsystem – Flash Parameters
        3. 7.9.5.3 Control Subsystem – Flash/OTP Access Timing
        4. 7.9.5.4 Control Subsystem – Flash Data Retention Duration
      6. 7.9.6 GPIO Electrical Data and Timing
        1. 7.9.6.1 GPIO - Output Timing
          1. 7.9.6.1.1 General-Purpose Output Switching Characteristics
        2. 7.9.6.2 GPIO - Input Timing
          1. 7.9.6.2.1 General-Purpose Input Timing Requirements
        3. 7.9.6.3 Sampling Window Width for Input Signals
        4. 7.9.6.4 Low-Power Mode Wakeup Timing
          1. 7.9.6.4.1 IDLE Mode Timing Requirements
          2. 7.9.6.4.2 IDLE Mode Switching Characteristics
          3. 7.9.6.4.3 IDLE Entry and Exit Timing Diagram
          4. 7.9.6.4.4 STANDBY Mode Timing Requirements
          5. 7.9.6.4.5 STANDBY Mode Switching Characteristics
          6. 7.9.6.4.6 STANDBY Entry and Exit Timing Diagram
          7. 7.9.6.4.7 HALT Mode Timing Requirements
          8. 7.9.6.4.8 HALT Mode Switching Characteristics
          9. 7.9.6.4.9 HALT Entry and Exit Timing Diagram
      7. 7.9.7 External Interrupt Electrical Data and Timing
        1. 7.9.7.1 External Interrupt Timing Requirements
        2. 7.9.7.2 External Interrupt Switching Characteristics
        3. 7.9.7.3 External Interrupt Timing Diagram
    10. 7.10 Analog and Shared Peripherals
      1. 7.10.1 Analog-to-Digital Converter
        1. 7.10.1.1 Sample Mode
        2. 7.10.1.2 Start-of-Conversion Triggers
        3. 7.10.1.3 Analog Inputs
        4. 7.10.1.4 ADC Result Registers and EOC Interrupts
        5. 7.10.1.5 ADC Electrical Data and Timing
          1. 7.10.1.5.1 ADC Electrical Characteristics
          2. 7.10.1.5.2 External ADC Start-of-Conversion Switching Characteristics
          3. 7.10.1.5.3 ADCSOCAO or ADCSOCBO Timing Diagram
      2. 7.10.2 Comparator + DAC Units
        1. 7.10.2.1 On-Chip Comparator and DAC Electrical Data and Timing
          1. 7.10.2.1.1 Electrical Characteristics of the Comparator/DAC
      3. 7.10.3 Interprocessor Communications
      4. 7.10.4 External Peripheral Interface
        1. 7.10.4.1 EPI General-Purpose Mode
        2. 7.10.4.2 EPI SDRAM Mode
        3. 7.10.4.3 EPI Host Bus Mode
          1. 7.10.4.3.1 EPI 8-Bit Host Bus (HB-8) Mode
            1. 7.10.4.3.1.1 HB-8 Muxed Address/Data Mode
            2. 7.10.4.3.1.2 HB-8 Non-Muxed Address/Data Mode
            3. 7.10.4.3.1.3 HB-8 FIFO Mode
          2. 7.10.4.3.2 EPI 16-Bit Host Bus (HB-16) Mode
            1. 7.10.4.3.2.1 HB-16 Muxed Address/Data Mode
            2. 7.10.4.3.2.2 HB-16 Non-Muxed Address/Data Mode
            3. 7.10.4.3.2.3 HB-16 FIFO Mode
        4. 7.10.4.4 EPI Electrical Data and Timing
          1. 7.10.4.4.1 EPI SDRAM Interface Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (see Figure 1-1 , Figure 1-1 , and Figure 1-1 )
          2. 7.10.4.4.2 EPI SDRAM Timing Diagrams
          3. 7.10.4.4.3 EPI Host-Bus 8 and Host-Bus 16 Interface Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (see Figure 1-1 , Figure 1-1 , Figure 1-1 , and Figure 1-1 )
          4. 7.10.4.4.4 EPI Host-Bus 8 and Host-Bus 16 Interface Timing Requirements (1) (see Figure 1-1 and Figure 1-1 )
          5. 7.10.4.4.5 EPI Host-Bus 8/16 Mode Timing Diagrams
          6. 7.10.4.4.6 EPI General-Purpose Interface Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (see Figure 1-1 )
          7. 7.10.4.4.7 EPI General-Purpose Interface Timing Requirements (see Figure 1-1 and Figure 1-1 )
          8. 7.10.4.4.8 EPI General-Purpose Interface Timing Diagrams
    11. 7.11 Master Subsystem Peripherals
      1. 7.11.1 Synchronous Serial Interface
        1. 7.11.1.1 Bit Rate Generation
        2. 7.11.1.2 Transmit FIFO
        3. 7.11.1.3 Receive FIFO
        4. 7.11.1.4 Interrupts
        5. 7.11.1.5 Frame Formats
      2. 7.11.2 Universal Asynchronous Receiver/Transmitter
        1. 7.11.2.1 Baud-Rate Generation
        2. 7.11.2.2 Transmit and Receive Logic
        3. 7.11.2.3 Data Transmission and Reception
        4. 7.11.2.4 Interrupts
      3. 7.11.3 Cortex-M3 Inter-Integrated Circuit
        1. 7.11.3.1 Functional Overview
        2. 7.11.3.2 Available Speed Modes
        3. 7.11.3.3 I2C Electrical Data and Timing
          1. 7.11.3.3.1 I2C Timing
      4. 7.11.4 Cortex-M3 Controller Area Network
        1. 7.11.4.1 Functional Overview
      5. 7.11.5 Cortex-M3 Universal Serial Bus Controller
        1. 7.11.5.1 Functional Description
      6. 7.11.6 Cortex-M3 Ethernet Media Access Controller
        1. 7.11.6.1 Functional Overview
        2. 7.11.6.2 MII Signals
        3. 7.11.6.3 EMAC Electrical Data and Timing
          1. 7.11.6.3.1 Timing Requirements for MIITXCK (see Figure 1-1 )
          2. 7.11.6.3.2 MIITXCK Timing Diagrams
          3. 7.11.6.3.3 Timing Requirements for MIIRXCK (see Figure 1-1 )
          4. 7.11.6.3.4 MIIRXCK Timing Diagram
          5. 7.11.6.3.5 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for EMAC MII Transmit (see Figure 1-1 )
          6. 7.11.6.3.6 EMAC MII Transmit Timing Diagram
          7. 7.11.6.3.7 Timing Requirements for EMAC MII Receive (see Figure 1-1 )
          8. 7.11.6.3.8 EMAC MII Receive Timing Diagram
        4. 7.11.6.4 MDIO Electrical Data and Timing
          1. 7.11.6.4.1 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for MDIO_CK (see Figure 1-1 )
          2. 7.11.6.4.2 MDIO_CK Timing Diagram
          3. 7.11.6.4.3 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for MDIO as Output (see Figure 1-1 )
          4. 7.11.6.4.4 MDIO as Output Timing Diagram
          5. 7.11.6.4.5 Timing Requirements for MDIO as Input (see Figure 1-1 )
          6. 7.11.6.4.6 MDIO as Input Timing Diagram
    12. 7.12 Control Subsystem Peripherals
      1. 7.12.1 High-Resolution PWM and Enhanced PWM Modules
        1. 7.12.1.1 HRPWM Electrical Data and Timing
          1. 7.12.1.1.1 High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz)
        2. 7.12.1.2 ePWM Electrical Data and Timing
          1. 7.12.1.2.1 ePWM Timing Requirements
          2. 7.12.1.2.2 ePWM Switching Characteristics
          3. 7.12.1.2.3 Trip-Zone Input Timing
            1. 7.12.1.2.3.1 Trip-Zone Input Timing Requirements
      2. 7.12.2 Enhanced Capture Module
        1. 7.12.2.1 eCAP Electrical Data and Timing
          1. 7.12.2.1.1 eCAP Timing Requirement
          2. 7.12.2.1.2 eCAP Switching Characteristics
      3. 7.12.3 Enhanced Quadrature Encoder Pulse Module
        1. 7.12.3.1 eQEP Electrical Data and Timing
          1. 7.12.3.1.1 eQEP Timing Requirements
          2. 7.12.3.1.2 eQEP Switching Characteristics
      4. 7.12.4 C28x Inter-Integrated Circuit Module
        1. 7.12.4.1 Functional Overview
        2. 7.12.4.2 Clock Generation
        3. 7.12.4.3 I2C Electrical Data and Timing
          1. 7.12.4.3.1 I2C Timing
      5. 7.12.5 C28x Serial Communications Interface
        1. 7.12.5.1 Architecture
        2. 7.12.5.2 Multiprocessor and Asynchronous Communication Modes
      6. 7.12.6 C28x Serial Peripheral Interface
        1. 7.12.6.1 Functional Overview
        2. 7.12.6.2 SPI Electrical Data and Timing
          1. 7.12.6.2.1 Master Mode Timing
            1. 7.12.6.2.1.1 SPI Master Mode External Timing (Clock Phase = 0)
            2. 7.12.6.2.1.2 SPI Master Mode External Timing (Clock Phase = 1)
          2. 7.12.6.2.2 Slave Mode Timing
            1. 7.12.6.2.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
            2. 7.12.6.2.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
      7. 7.12.7 C28x Multichannel Buffered Serial Port
        1. 7.12.7.1 McBSP Electrical Data and Timing
          1. 7.12.7.1.1 McBSP Transmit and Receive Timing
            1. 7.12.7.1.1.1 McBSP Timing Requirements
            2. 7.12.7.1.1.2 McBSP Switching Characteristics
            3. 7.12.7.1.1.3 McBSP Timing Diagrams
          2. 7.12.7.1.2 McBSP as SPI Master or Slave Timing
            1. 7.12.7.1.2.1  McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. 7.12.7.1.2.2  McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 10b, CLKXP = 0)
            3. 7.12.7.1.2.3  McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 Timing Diagram
            4. 7.12.7.1.2.4  McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            5. 7.12.7.1.2.5  McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 11b, CLKXP = 0)
            6. 7.12.7.1.2.6  McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 Timing Diagram
            7. 7.12.7.1.2.7  McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            8. 7.12.7.1.2.8  McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 10b, CLKXP = 1)
            9. 7.12.7.1.2.9  McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 Timing Diagram
            10. 7.12.7.1.2.10 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            11. 7.12.7.1.2.11 McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (CLKSTP = 11b, CLKXP = 1)
            12. 7.12.7.1.2.12 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 Timing Diagram
  8. 8 Detailed Description
    1. 8.1  Memory Maps
      1. 8.1.1 Control Subsystem Memory Map
      2. 8.1.2 Master Subsystem Memory Map
    2. 8.2  Identification
    3. 8.3  Master Subsystem
      1. 8.3.1 Cortex-M3 CPU
      2. 8.3.2 Cortex-M3 DMA and NVIC
      3. 8.3.3 Cortex-M3 Interrupts
      4. 8.3.4 Cortex-M3 Vector Table
      5. 8.3.5 Cortex-M3 Local Peripherals
      6. 8.3.6 Cortex-M3 Local Memory
      7. 8.3.7 Cortex-M3 Accessing Shared Resources and Analog Peripherals
    4. 8.4  Control Subsystem
      1. 8.4.1 C28x CPU/FPU/VCU
      2. 8.4.2 C28x Core Hardware Built-In Self-Test
      3. 8.4.3 C28x Peripheral Interrupt Expansion
      4. 8.4.4 C28x Direct Memory Access
      5. 8.4.5 C28x Local Peripherals
      6. 8.4.6 C28x Local Memory
      7. 8.4.7 C28x Accessing Shared Resources and Analog Peripherals
    5. 8.5  Analog Subsystem
      1. 8.5.1 ADC1
      2. 8.5.2 ADC2
      3. 8.5.3 Analog Comparator + DAC
      4. 8.5.4 Analog Common Interface Bus
    6. 8.6  Master Subsystem NMIs
    7. 8.7  Control Subsystem NMIs
    8. 8.8  Resets
      1. 8.8.1 Cortex-M3 Resets
      2. 8.8.2 C28x Resets
      3. 8.8.3 Analog Subsystem and Shared Resources Resets
      4. 8.8.4 Device Boot Sequence
    9. 8.9  Internal Voltage Regulation and Power-On-Reset Functionality
      1. 8.9.1 Analog Subsystem: Internal 1.8-V VREG
      2. 8.9.2 Digital Subsystem: Internal 1.2-V VREG
      3. 8.9.3 Analog and Digital Subsystems: Power-On-Reset Functionality
      4. 8.9.4 Connecting ARS and XRS Pins
    10. 8.10 Input Clocks and PLLs
      1. 8.10.1 Internal Oscillator (Zero-Pin)
      2. 8.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC)
      3. 8.10.3 External Oscillators (Pins X1 and XCLKIN)
      4. 8.10.4 Main PLL
      5. 8.10.5 USB PLL
    11. 8.11 Master Subsystem Clocking
      1. 8.11.1 Cortex-M3 Run Mode
      2. 8.11.2 Cortex-M3 Sleep Mode
      3. 8.11.3 Cortex-M3 Deep Sleep Mode
    12. 8.12 Control Subsystem Clocking
      1. 8.12.1 C28x Normal Mode
      2. 8.12.2 C28x IDLE Mode
      3. 8.12.3 C28x STANDBY Mode
    13. 8.13 Analog Subsystem Clocking
    14. 8.14 Shared Resources Clocking
    15. 8.15 Loss of Input Clock (NMI Watchdog Function)
    16. 8.16 GPIOs and Other Pins
      1. 8.16.1 GPIO_MUX1
      2. 8.16.2 GPIO_MUX2
      3. 8.16.3 AIO_MUX1
      4. 8.16.4 AIO_MUX2
    17. 8.17 Emulation/JTAG
    18. 8.18 Code Security Module
      1. 8.18.1 Functional Description
    19. 8.19 µCRC Module
      1. 8.19.1 Functional Description
      2. 8.19.2 CRC Polynomials
      3. 8.19.3 CRC Calculation Procedure
      4. 8.19.4 CRC Calculation for Data Stored In Secure Memory
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Device and Development Support Tool Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Trademarks
    5. 10.5 サポート・リソース
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.2.1 Signal Descriptions

TERMINAL(1) I/O/Z(2) DESCRIPTION PU
or
PD(3)		 OUTPUT
BUFFER
STRENGTH
NAME RFP
PIN NO.
ADC 1 Reference Inputs, Analog Comparator Inputs, DAC Inputs, AIO Group 1
ADC1VREFHI 120 I ADC1 External High Reference – used only when in ADC external reference mode.
ADC1VREFLO see VSSA1 I ADC1 External Low Reference – used only when in ADC external reference mode.
ADC1INA0 121 I ADC1 Group A, Channel 0 input
ADC1INA2 122 I ADC1 Group A, Channel 2 input 4 mA
COMPA1 I Comparator Input A1
AIO2 I/O Digital AIO2
ADC1INA3 123 I ADC1 Group A, Channel 3 input
ADC1INA4 124 I ADC1 Group A, Channel 4 input 4 mA
COMPA2 I Comparator Input A2
AIO4 I/O Digital AIO4
ADC1INA6 125 I ADC1 Group A, Channel 6 input 4 mA
COMPA3 I Comparator Input A3
AIO6 I/O Digital AIO6
ADC1INA7 126 I ADC1 Group A, Channel 7 input
ADC1INB0 117 I ADC1 Group B, Channel 0 input
ADC1INB3 116 I ADC1 Group B, Channel 3 input
ADC1INB4 115 I ADC1 Group B, Channel 4 input 4 mA
COMPB2 I Comparator Input B2
AIO12 I/O Digital AIO12
ADC1INB7 114 I ADC1 Group B, Channel 7 input
ADC 2 Reference Inputs, Analog Comparator Inputs, DAC Inputs, AIO Group 2
ADC2VREFHI 133 I ADC2 External High Reference – used only when in ADC external reference mode.
ADC2VREFLO see VSSA2 I ADC2 External Low Reference – used only when in ADC external reference mode.
ADC2INA0 132 I ADC2 Group A, Channel 0 input
ADC2INA2 131 I ADC2 Group A, Channel 2 input 4 mA
COMPA4 I Comparator Input A4
AIO18 I/O Digital AIO18
ADC2INA3 130 I ADC2 Group A, Channel 3 input
ADC2INA4 129 I ADC2 Group A, Channel 4 input 4 mA
COMPA5 I Comparator Input A5
AIO20 I/O Digital AIO20
ADC2INA6 128 I ADC2 Group A, Channel 6 input 4 mA
COMPA6 I Comparator Input A6
AIO22 I/O Digital AIO22
ADC2INA7 127 I ADC2 Group A, Channel 7 input
ADC2INB0 136 I ADC2 Group B, Channel 0 input
ADC2INB3 137 I ADC2 Group B, Channel 3 input
ADC2INB4 138 I ADC2 Group B, Channel 4 input 4 mA
COMPB5 I Comparator Input B5
AIO28 I/O Digital AIO28
ADC2INB7 139 I ADC2 Group B, Channel 7 input
ADC Modules Analog Power and Ground
VDDA1 119 3.3-V Analog Module 1 Power Pin. Tie with
a 2.2-µF capacitor (typical) close to the pin.
VDDA2 134 3.3-V Analog Module 2 Power Pin. Tie with
a 2.2-µF capacitor (typical) close to the pin.
VSSA1 118 Analog ground for ADC1, ADC1VREFLO, COMP1–3, and DAC1–3
VSSA2 135 Analog ground for ADC2, ADC2VREFLO, COMP4–6, and DAC4–6
Analog Comparator Results (Digital) and GPIO Group 2 (C28x Access Only)
GPIO128 140 I/O General-purpose input/output 128 PU 4 mA
GPIO129 141 I/O General-purpose input/output 129 PU 4 mA
COMP1OUT O Compare result from Analog Comparator 1
GPIO130 142 I/O General-purpose input/output 130 PU 4 mA
COMP6OUT O Compare result from Analog Comparator 6
GPIO131 143 I/O General-purpose input/output 131 PU 4 mA
COMP2OUT O Compare result from Analog Comparator 2
GPIO132 112 I/O General-purpose input/output 132 PU 8 mA
COMP3OUT O Compare result from Analog Comparator 3
GPIO133 111 I/O General-purpose input/output 133 PU 4 mA
COMP4OUT O Compare result from Analog Comparator 4
GPIO134 110 I/O General-purpose input/output 134 PU 4 mA
GPIO135(4) 109 I/O General-purpose input/output 135 PU 8 mA
COMP5OUT O Compare result from Analog Comparator 5
GPIO Group 1 and Peripheral Signals
PA0_GPIO0 5 I/O/Z General-purpose input/output 0 PU 4 mA
M_U0RX I UART-0 receive data
M_I2C1SCL I/OD I2C-1 clock open-drain bidirectional port
M_U1RX I UART-1 receive data
C_EPWM1A O Enhanced PWM-1 output A
PA1_GPIO1 6 I/O/Z General-purpose input/output 1 PU 4 mA
M_U0TX O UART-0 transmit data
M_I2C1SDA I/OD I2C-1 data open-drain bidirectional port
M_U1TX O UART-1 data transmit
M_SSI1FSS I/O SSI-1 frame
C_EPWM1B O Enhanced PWM-1 output B
C_ECAP6 I/O Enhanced Capture-6 input/output
PA2_GPIO2 7 I/O/Z General-purpose input/output 2 PU 4 mA
M_SSI0CLK I/O SSI-0 clock
M_MIITXD2 O EMAC MII transmit data bit 2
C_EPWM2A O Enhanced PWM-2 output A
PA3_GPIO3 8 I/O/Z General-purpose input/output 3 PU 4 mA
M_SSI0FSS I/O SSI-0 frame
M_MIITXD1 O EMAC MII transmit data bit 1
M_SSI1CLK I/O SSI-1 clock
C_EPWM2B O Enhanced PWM-2 output B
C_ECAP5 I/O Enhanced Capture-5 input/output
PA4_GPIO4 9 I/O/Z General-purpose input/output 4 PU 4 mA
M_SSI0RX I SSI-0 receive data
M_MIITXD0 O EMAC MII transmit data bit 0
M_CAN0RX I CAN-0 receive data
C_EPWM3A O Enhanced PWM-3 output A
PA5_GPIO5 12 I/O/Z General-purpose input/output 5 PU 4 mA
M_SSI0TX O SSI-0 transmit data
M_MIIRXDV I EMAC MII receive data valid
M_CAN0TX O CAN-0 transmit data
C_EPWM3B O Enhanced PWM-3 output B
C_MFSRA I McBSP-A receive frame sync
C_ECAP1 I/O Enhanced Capture-1 input/output
PA6_GPIO6 13 I/O/Z General-purpose input/output 6 PU 4 mA
M_I2C1SCL I/OD I2C-1 clock open-drain bidirectional port
M_CCP1 I/O Capture/Compare/PWM-1
(General-purpose Timer)
M_MIIRXCK I EMAC MII receive clock
M_CAN0RX I CAN-0 receive data
M_USB0EPEN O USB-0 external power enable
(optionally used in host mode)
M_MIITXD3 O EMAC MII transmit data bit 3
C_EPWM4A O Enhanced PWM-4 output A
C_EPWMSYNCO O Enhanced PWM-4 external sync pulse
PA7_GPIO7 14 I/O/Z General-purpose input/output 7 PU 4 mA
M_I2C1SDA I/OD I2C-1 data open-drain bidirectional port
M_CCP4 I/O Capture/Compare/PWM-4
(General-purpose Timer)
M_MIIRXER I EMAC MII receive error
M_CAN0TX O CAN-0 transmit data
M_CCP3 I/O Capture/Compare/PWM-3
(General-purpose Timer)
M_USB0PFLT I USB-0 external power error state
(optionally used in the host mode)
M_MIIRXD1 I EMAC MII receive data 1
C_EPWM4B O Enhanced PWM-4 output B
C_MCLKRA I McBSP-A receive clock
C_ECAP2 I/O Enhanced Capture-1 input/output
PB0_GPIO8 15 I/O/Z General-purpose input/output 8 PU 4 mA
M_CCP0 I/O Capture/Compare/PWM-0
(General-purpose Timer)
M_U1RX I UART-1 data receive data
M_SSI2TX O SSI-2 transmit data
M_CAN1TX O CAN-1 transmit data
M_U4TX O UART-4 transmit data
C_EPWM5A O Enhanced PWM-5 output A
C_ADCSOCAO O ADC start-of-conversion A
PB1_GPIO9 18 I/O/Z General-purpose input/output 9 PU 4 mA
M_CCP2 I/O Capture/Compare/PWM-2
(General-purpose Timer)
M_CCP1 I/O Capture/Compare/PWM-1
(General-purpose Timer)
M_U1TX O UART-1 transmit data
M_SSI2RX I SSI-2 receive data
C_EPWM5B O Enhanced PWM-5 output B
C_ECAP3 I/O Enhanced Capture-3 input/output
PB2_GPIO10 19 I/O/Z General-purpose input/output 10 PU 4 mA
M_I2C0SCL I/OD I2C-0 clock open-drain bidirectional port
M_CCP3 I/O Capture/Compare/PWM-3
(General-purpose Timer)
M_CCP0 I/O Capture/Compare/PWM-0
(General-purpose Timer)
M_USB0EPEN O USB-0 external power enable
(optionally used in the host mode)
M_SSI2CLK I/O SSI-2 clock
M_CAN1RX I CAN-1 receive data
M_U4RX I UART-4 receive data
C_EPWM6A O Enhanced PWM-6 output A
C_ADCSOCBO O ADC start-of-conversion B
PB3_GPIO11 20 I/O/Z General-purpose input/output 11 PU 4 mA
M_I2C0SDA I/OD I2C-0 data open-drain bidirectional port
M_USB0PFLT I USB-0 external power error state
(optionally used in the host mode)
M_SSI2FSS I/O SSI-2 frame
M_U1RX I UART-1 receive data
C_EPWM6B O Enhanced PWM-6 output B
C_ECAP4 I/O Enhanced Capture-4 input/output
PB4_GPIO12 30 I/O/Z General-purpose input/output 12 PU 4 mA
M_U2RX I UART-2 receive data
M_CAN0RX I CAN-0 receive data
M_U1RX I UART-1 receive data
M_EPI0S23 I/O EPI-0 signal 23
M_CAN1TX O CAN-1 transmit data
M_SSI1TX O SSI-1 transmit data
C_EPWM7A O Enhanced PWM-7 output A
PB5_GPIO13 31 I/O/Z General-purpose input/output 13 PU 4 mA
M_CCP5 I/O Capture/Compare/PWM-5
(General-purpose Timer)
M_CCP6 I/O Capture/Compare/PWM-6
(General-purpose Timer)
M_CCP0 I/O Capture/Compare/PWM-0
(General-purpose Timer)
M_CAN0TX O CAN-0 transmit data
M_CCP2 I/O Capture/Compare/PWM-2
(General-purpose Timer)
M_U1TX O UART-1 transmit data
M_EPI0S22 I/O EPI-0 signal 22
M_CAN1RX I CAN-1 receive data
M_SSI1RX I SSI-1 receive data
C_EPWM7B O Enhanced PWM-7 output B
PB6_GPIO14 26 I/O/Z General-purpose input/output 14 PU 4 mA
M_CCP1 I/O Capture/Compare/PWM-1
(General-purpose Timer)
M_CCP7 I/O Capture/Compare/PWM-7
(General-purpose Timer)
M_CCP5 I/O Capture/Compare/PWM-5
(General-purpose Timer)
M_EPI0S37(5) I/O EPI-0 signal 37
M_MIICRS I EMAC MII carrier sense
M_I2C0SDA I/OD I2C-0 data open-drain bidirectional port
M_U1TX O UART-1 transmit data
M_SSI1CLK I/O SSI-1 clock
C_EPWM8A O Enhanced PWM-8 output A
PB7_GPIO15 27 I/O/Z General-purpose input/output 15 PU 4 mA
M_EXTNMI I Cortex-M3 external nonmaskable interrupt
M_MIIRXD1 I EMAC MII receive data 1
M_EPI0S36(5) I/O EPI-0 signal 36
M_I2C0SCL I/OD I2C-0 clock open-drain bidirectional port
M_U1RX I UART-1 receive data
M_SSI1FSS I/O SSI-1 frame
C_EPWM8B O Enhanced PWM-8 output B
PD0_GPIO16 102 I/O/Z General-purpose input/output 16 PU 4 mA
M_CAN0RX I CAN-0 receive data
M_U2RX I UART-2 receive data
M_U1RX I UART-1 receive data
M_CCP6 I/O Capture/Compare/PWM-6
(General-purpose Timer)
M_MIIRXDV I EMAC MII receive data valid
M_MIIRXD2 I EMAC MII receive data 2
M_SSI0TX O SSI-0 transmit data
M_CAN1TX O CAN-1 transmit data
M_USB0EPEN O USB-0 external power enable
(optionally used in the host mode)
C_SPISIMOA I/O SPI-A slave in, master out
PD1_GPIO17 98 I/O/Z General-purpose input/output 17 PU 4 mA
M_CAN0TX O CAN-0 transmit data
M_U2TX O UART-2 transmit data
M_U1TX O UART-1 transmit data
M_CCP7 I/O Capture/Compare/PWM-7
(General-purpose Timer)
M_MIITXER O EMAC MII transmit error
M_CCP2 I/O Capture/Compare/PWM-2
(General-purpose Timer)
M_MIICOL I EMAC MII collision detect
M_SSI0RX I SSI-0 receive data
M_CAN1RX I CAN-1 receive data
M_USB0PFLT I USB-0 external power error state
(optionally used in the host mode)
C_SPISOMIA I/O SPI-A master in, slave out
PD2_GPIO18 28 I/O/Z General-purpose input/output 18 PU 4 mA
M_U1RX I UART-1 receive data
M_CCP6 I/O Capture/Compare/PWM-6
(General-purpose Timer)
M_CCP5 I/O Capture/Compare/PWM-5
(General-purpose Timer)
M_EPI0S20 I/O EPI-0 signal 20
M_SSI0CLK I/O SSI-0 clock
M_U1TX O UART-1 transmit data
M_CAN0RX I CAN-0 receive data
C_SPICLKA I/O SPI-A clock
PD3_GPIO19 29 I/O/Z General-purpose input/output 19 PU 4 mA
M_U1TX O UART-1 transmit data
M_CCP7 I/O Capture/Compare/PWM-7
(General-purpose Timer)
M_CCP0 I/O Capture/Compare/PWM-0
(General-purpose Timer)
M_EPI0S21 I/O EPI-0 signal 21
M_SSI0FSS I/O SSI-0 frame
M_U1RX I UART-1 receive data
M_CAN0TX O CAN-0 transmit data
C_SPISTEA I/O SPI-A slave transmit enable
PD4_GPIO20 65 I/O/Z General-purpose input/output 20 PU 4 mA
M_CCP0 I/O Capture/Compare/PWM-0
(General-purpose Timer)
M_CCP3 I/O Capture/Compare/PWM-3
(General-purpose Timer)
M_MIITXD3 O EMAC MII transmit data 3
M_EPI0S19 I/O EPI-0 signal 19
M_U3TX O UART-3 transmit data
M_CAN1TX O CAN-1 transmit data
C_EQEP1A I Enhanced QEP-1 input A
C_MDXA O McBSP-A transmit data
PD5_GPIO21 64 I/O/Z General-purpose input/output 21 PU 6 mA
M_CCP2 I/O Capture/Compare/PWM-2
(General-purpose Timer)
M_CCP4 I/O Capture/Compare/PWM-4
(General-purpose Timer)
M_MIITXD2 O EMAC MII transmit data 2
M_U2RX I UART-2 receive data
M_EPI0S28 I/O EPI-0 signal 28
M_U3RX I UART-3 receive data
M_CAN1RX I CAN-1 receive data
C_EQEP1B I Enhanced QEP-1 input B
C_MDRA I McBSP-A receive data
PD6_GPIO22 73 I/O/Z General-purpose input/output 22 PU 6 mA
M_MIITXD1 O EMAC MII transmit data 1
M_U2TX O UART-2 transmit data
M_EPI0S29 I/O EPI-0 signal 29
M_I2C1SDA I/OD I2C-0 data open-drain bidirectional port
M_U1TX O UART-1 transmit data
C_EQEP1S I/O Enhanced QEP-1 strobe
C_MCLKXA O McBSP-A transmit clock
PD7_GPIO23 68 I/O/Z General-purpose input/output 23 PU 6 mA
M_CCP1 I/O Capture/Compare/PWM-1
(General-purpose Timer)
M_MIITXD0 O EMAC MII transmit data 0
M_EPI0S30 I/O EPI-0 signal 30
M_I2C1SCL I/OD I2C-1 clock open-drain bidirectional port
M_U1RX I UART-1 receive data
C_EQEP1I I/O Enhanced QEP-1 index
C_MFSXA O McBSP-A transmit frame sync
PE0_GPIO24 43 I/O/Z General-purpose input/output 24 PU 4 mA
M_SSI1CLK I/O SSI-1 clock
M_CCP3 I/O Capture/Compare/PWM-3
(General-purpose Timer)
M_EPI0S8 I/O EPI-0 signal 8
M_USB0PFLT I USB-0 external power error state
(optionally used in the host mode)
M_SSI3TX O SSI-3 transmit data
M_CAN0RX I CAN-1 receive data
M_SSI1TX O SSI-1 transmit data
C_ECAP1 I/O Enhanced Capture-1 input/output
C_EQEP2A I Enhanced QEP-2 input A
PE1_GPIO25 45 I/O/Z General-purpose input/output 25 PU 4 mA
M_SSI1FSS I/O SSI-1 frame
M_CCP2 I/O Capture/Compare/PWM-2
(General-purpose Timer)
M_CCP6 I/O Capture/Compare/PWM-6
(General-purpose Timer)
M_EPI0S9 I/O EPI-0 signal 9
M_SSI3RX I SSI-3 receive data
M_CAN0TX O CAN-1 transmit data
M_SSI1RX O SSI-1 receive data
C_ECAP2 I/O Enhanced Capture-2 input/output
C_EQEP2B I Enhanced QEP-2 input B
PE2_GPIO26 32 I/O/Z General-purpose input/output 26 PU 4 mA
M_CCP4 I/O Capture/Compare/PWM-4
(General-purpose Timer)
M_SSI1RX I SSI-1 receive data
M_CCP2 I/O Capture/Compare/PWM-2
(General-purpose Timer)
M_EPI0S24 I/O EPI-0 signal 24
M_SSI3CLK I/O SSI-3 clock
M_U2RX I UART-2 receive data
M_SSI1CLK I/O SSI-1 clock
C_ECAP3 I/O Enhanced Capture-3 input/output
C_EQEP2I I/O Enhanced QEP-2 index
PE3_GPIO27 33 I/O/Z General-purpose input/output 27 PU 4 mA
M_CCP1 I/O Capture/Compare/PWM-1
(General-purpose Timer)
M_SSI1TX O SSI-1 transmit data
M_CCP7 I/O Capture/Compare/PWM-7
(General-purpose Timer)
M_EPI0S25 I/O EPI-0 signal 25
M_SSI3FSS I/O SSI-3 frame
M_U2TX O UART-2 transmit data
M_SSI1FSS I/O SSI-1 frame
C_ECAP4 I/O Enhanced Capture-4 input/output
C_EQEP2S I/O Enhanced QEP-2 strobe
PE4_GPIO28 77 I/O/Z General-purpose input/output 28 PU 4 mA
M_CCP3 I/O Capture/Compare/PWM-3
(General-purpose Timer)
M_U2TX O UART-2 transmit data
M_CCP2 I/O Capture/Compare/PWM-2
(General-purpose Timer)
M_MIIRXD0 I EMAC MII receive data 0
M_EPI0S34(5) I/O EPI-0 signal 34
M_U0RX I UART-0 receive data
M_EPI0S38(5) I/O EPI-0 signal 38
M_USB0EPEN O USB-0 external power enable
(optionally used in the host mode)
C_SCIRXDA I SCI-A receive data
PE5_GPIO29 76 I/O/Z General-purpose input/output 29 PU 4 mA
M_CCP5 I/O Capture/Compare/PWM-5
(General-purpose Timer)
M_EPI0S35(5) I/O EPI-0 signal 35
M_MIITXER O EMAC MII transmit error
M_U0TX O UART-0 transmit data
M_USB0PFLT I USB-0 external power error state
(optionally used in the host mode)
C_SCITXDA O SCI-A transmit data
PE6_GPIO30 22 I/O/Z General-purpose input/output 30 PU 4 mA
M_MIIMDIO I/O EMAC management data input/output
M_CAN0RX I CAN-0 receive data
C_EPWM9A O Enhanced PWM-9 output A
PE7_GPIO31 23 I/O/Z General-purpose input/output 31 PU 4 mA
M_MIIRXD3 I EMAC MII receive data 3
M_CAN0TX O CAN-0 transmit data
C_EPWM9B O Enhanced PWM-9 output B
PF0_GPIO32 104 I/O/Z General-purpose input/output 32 PU 4 mA
M_CAN1RX I CAN-1 receive data
M_MIIRXCK I EMAC MII receive clock
M_I2C0SDA I/OD I2C-0 data open-drain bidirectional port
M_TRACED2 O Trace data 2
C_I2CASDA I/OD I2C-A data open-drain bidirectional port
C_SCIRXDA I SCI-A receive data
C_ADCSOCAO O ADC start-of-conversion A(6)
PF1_GPIO33 103 I/O/Z General-purpose input/output 33 PU 4 mA
M_CAN1TX O CAN-1 transmit data
M_MIIRXER I EMAC MII receive error
M_CCP3 I/O Capture/Compare/PWM-3
(General-purpose Timer)
M_I2C0SCL I/OD I2C-0 clock open-drain bidirectional port
M_TRACED3 O Trace data 3
C_I2CASCL I/OD I2C-A clock open-drain bidirectional port
C_EPWMSYNCO O Enhanced PWM sync out
C_ADCSOCBO O ADC start-of-conversion B(6)
PF2_GPIO34 82 I/O/Z General-purpose input/output 34 PU 4 mA
M_MIIPHYINTR I EMAC PHY MII interrupt
M_EPI0S32(5) I/O EPI-0 signal 32
M_SSI1CLK I/O SSI-1 clock
M_TRACECLK O Trace clock
M_XCLKOUT O External output clock
C_ECAP1 I/O Enhanced Capture-1 input/output
C_SCIRXDA I SCI-A receive data
C_XCLKOUT O External output clock
Bmode_pin4 I Boot mode pin 4
PF3_GPIO35 81 I/O/Z General-purpose input/output 35 PU 4 mA
M_MIIMDC I EMAC management data clock
M_EPI0S33(5) I/O EPI-0 signal 33
M_SSI1FSS I/O SSI-1 frame
M_U0TX O UART-0 transmit data
M_TRACED0 O Trace data 0
C_SCITXDA O SCI-A transmit data
Bmode_pin3 I Boot mode pin 3
PF4_GPIO36 48 I/O/Z General-purpose input/output 36 PU 4 mA
M_CCP0 I/O Capture/Compare/PWM-0
(General-purpose Timer)
M_MIIMDIO I/O EMAC management data input/output
M_EPI0S12 I/O EPI-0 signal 12
M_SSI1RX I SSI-1 receive data
M_U0RX I UART-0 receive data
C_SCIRXDA I SCI-A receive data
PF5_GPIO37 51 I/O/Z General-purpose input/output 37 PU 4 mA
M_CCP2 I/O Capture/Compare/PWM-2
(General-purpose Timer)
M_MIIRXD3 I EMAC MII receive data 3
M_EPI0S15 I/O EPI-0 signal 15
M_SSI1TX O SSI-1 transmit data
C_ECAP2 I/O Enhanced Capture-2 input/output
PF6_GPIO38 69 I/O/Z General-purpose input/output 38. If configured as an output, place a capacitor with a value of 56 pF or greater near the pin. If configured as an input, place a series resistor with a value equal to 1 kΩ or greater near the pin. See the F28M35x Concerto™ MCUs Silicon Errata for details.
NOTE: For this pin, only the USB0VBUS function is available on silicon revision 0 devices (GPIO and the four other functions listed are not available).		 PU 4 mA
M_USB0VBUS Analog USB0 VBUS power (5-V tolerant)
M_CCP1 I/O Capture/Compare/PWM-1
(General-purpose Timer)
M_MIIRXD2 I EMAC MII receive data 2
M_EPI0S38(5) I/O EPI-0 signal 38
PF7_GPIO39 No Pin No Pin General-purpose input/output 39 is not pinned out.
PG0_GPIO40 49 I/O/Z General-purpose input/output 40 PU 4 mA
M_U2RX I UART-2 receive data
M_I2C1SCL I/OD I2C-1 clock open-drain bidirectional port
M_USB0EPEN O USB-0 external power enable
(optionally used in the host mode)
M_EPI0S13 I/O EPI-0 signal 13
M_MIIRXD2 I EMAC MII receive data 2
M_U4RX I UART-4 receive data
PG1_GPIO41 50 I/O/Z General-purpose input/output 41 PU 4 mA
M_U2TX O UART-2 transmit data
M_I2C1SDA I/OD I2C-1 data open-drain bidirectional port
M_EPI0S14 I/O EPI-0 signal 14
M_MIIRXD1 I EMAC MII receive data 1
M_U4TX O UART-4 transmit data
PG2_GPIO42 71 I/O/Z General-purpose input/output 42 PU 4 mA
M_USB0DM Analog USB0 data minus
M_MIICOL I EMAC MII collision detect
M_EPI0S39(5) I/O EPI-0 signal 39
PG3_GPIO43 78 I/O/Z General-purpose input/output 43 PU 4 mA
M_MIICRS I EMAC MII carrier sense
M_MIIRXDV I EMAC MII receive data valid
M_TRACED1 O Trace data 1
Bmode_pin1 I Boot mode pin 1
PG4_GPIO44 No Pin No Pin General-purpose input/output 44 is not pinned out.
PG5_GPIO45 72 I/O/Z General-purpose input/output 45 PU 4 mA
M_USB0DP Analog USB0 data plus
M_CCP5 I/O Capture/Compare/PWM-5
(General-purpose Timer)
M_MIITXEN O EMAC MII transmit enable
M_EPI0S40(5) I/O EPI-0 signal 40
PG6_GPIO46 70 I/O/Z General-purpose input/output 46. If configured as an output, place a capacitor with a value of 56 pF or greater near the pin. If configured as an input, place a series resistor with a value equal to 1 kΩ or greater near the pin. See the F28M35x Concerto™ MCUs Silicon Errata for details.
NOTE: For this pin, only the USB0ID function is available on silicon revision 0 devices (GPIO and the three other functions listed are not available).		 PU 4 mA
M_USB0ID Analog USB0 ID (5-V tolerant)
M_MIITXCK I EMAC MII transmit clock
M_EPI0S41(5) I/O EPI-0 signal 41
PG7_GPIO47 52 I/O/Z General-purpose input/output 47 PU 6 mA
M_MIITXER O EMAC MII transmit error
M_CCP5 I/O Capture/Compare/PWM-5
(General-purpose Timer)
M_EPI0S31 I/O EPI-0 signal 31
Bmode_pin2 I Boot mode pin 2
PH0_GPIO48 41 I/O/Z General-purpose input/output 48 PU 4 mA
M_CCP6 I/O Capture/Compare/PWM-6
(General-purpose Timer)
M_MIIPHYRST O EMAC PHY MII reset
M_EPI0S6 I/O EPI-0 signal 6
M_SSI3TX O SSI-3 transmit data
C_ECAP5 I/O Enhanced Capture-5 input/output
PH1_GPIO49 42 I/O/Z General-purpose input/output 49 PU 4 mA
M_CCP7 I/O Capture/Compare/PWM-7
(General-purpose Timer)
M_EPI0S7 I/O EPI-0 signal 7
M_MIIRXD0 I EMAC MII receive data 0
M_SSI3RX I SSI-3 receive data
C_ECAP6 I/O Enhanced Capture-6 input/output
PH2_GPIO50 36 I/O/Z General-purpose input/output 50 PU 4 mA
M_EPI0S1 I/O EPI-0 signal 1
M_MIITXD3 O EMAC MII transmit data 3
M_SSI3CLK I/O SSI-3 clock
C_EQEP1A I Enhanced QEP-1 input A
PH3_GPIO51 35 I/O/Z General-purpose input/output 51 PU 4 mA
M_USB0EPEN O USB-0 external power enable
(optionally used in the host mode)
M_EPI0S0 I/O EPI-0 signal 0
M_MIITXD2 O EMAC MII transmit data 2
M_SSI3FSS I/O SSI-3 frame
C_EQEP1B I Enhanced QEP-1 input B
PH4_GPIO52 46 I/O/Z General-purpose input/output 52 PU 4 mA
M_USB0PFLT I USB-0 external power error state
(optionally used in the host mode)
M_EPI0S10 I/O EPI-0 signal 10
M_MIITXD1 O EMAC MII transmit data 1
M_SSI1CLK I/O SSI-1 clock
M_U3TX O UART-3 transmit data
C_EQEP1S I/O Enhanced QEP-1 strobe
PH5_GPIO53 47 I/O/Z General-purpose input/output 53 PU 4 mA
M_EPI0S11 I/O EPI-0 signal 11
M_MIITXD0 O EMAC MII transmit data 0
M_SSI1FSS I/O SSI-1 frame
M_U3RX I UART-3 receive data
C_EQEP1I I/O Enhanced QEP-1 index
PH6_GPIO54 79 I/O/Z General-purpose input/output 54 PU 4 mA
M_EPI0S26 I/O EPI-0 signal 26
M_MIIRXDV I EMAC MII receive data valid
M_SSI1RX I SSI-1 receive data
M_MIITXEN O EMAC MII transmit enable
M_SSI0TX O SSI-0 transmit data
C_SPISIMOA I/O SPI-A slave in, master out
C_EQEP3A I Enhanced QEP-1 input A
PH7_GPIO55 80 I/O/Z General-purpose input/output 55 PU 4 mA
M_MIIRXCK I EMAC MII receive clock
M_EPI0S27 I/O EPI-0 signal 27
M_SSI1TX O SSI-1 transmit data
M_MIITXCK I EMAC MII transmit clock
M_SSI0RX I SSI-0 receive data
C_SPISOMIA I/O SPI-A master in, slave out
C_EQEP3B I Enhanced QEP-3 input B
PJ0_GPIO56 63 I/O/Z General-purpose input/output 56 PU 4 mA
M_MIIRXER I EMAC MII receive error
M_EPI0S16 I/O EPI-0 signal 16
M_I2C1SCL I/OD I2C-1 clock open-drain bidirectional port
M_SSI0CLK I/O SSI-0 clock
C_SPICLKA I/O SPI-A clock
C_EQEP3S I/O Enhanced QEP-3 strobe
PJ1_GPIO57 62 I/O/Z General-purpose input/output 57 PU 4 mA
M_EPI0S17 I/O EPI-0 signal 17
M_USB0PFLT I USB-0 external power error state
(optionally used in the host mode)
M_I2C1SDA I/OD I2C-1 data open-drain bidirectional port
M_MIIRXDV I EMAC MII receive data valid
M_SSI0FSS I/O SSI-0 frame
C_SPISTEA I/O SPI-A slave transmit enable
C_EQEP3I I/O Enhanced QEP-3 index
PJ2_GPIO58 61 I/O/Z General-purpose input/output 58 PU 4 mA
M_EPI0S18 I/O EPI-0 signal 18
M_CCP0 I/O Capture/Compare/PWM-0
(General-purpose Timer)
M_MIIRXCK I EMAC MII receive clock
M_SSI0CLK I/O SSI-0 clock
M_U0TX O UART-0 transmit data
C_MCLKRA I McBSP-A receive clock
C_EPWM7A O Enhanced PWM-7 output A
PJ3_GPIO59 60 I/O/Z General-purpose input/output 59 PU 4 mA
M_EPI0S19 I/O EPI-0 signal 19
M_CCP6 I/O Capture/Compare/PWM-6
(General-purpose Timer)
M_MIIMDC O EMAC management data clock
M_SSI0FSS I/O SSI-0 frame
M_U0RX I UART-0 receive data
C_MFSRA I McBSP-A receive frame sync
C_EPWM7B O Enhanced PWM-7 output B
PJ4_GPIO60 57 I/O/Z General-purpose input/output 60 PU 6 mA
M_EPI0S28 I/O EPI-0 signal 28
M_CCP4 I/O Capture/Compare/PWM-4
(General-purpose Timer)
M_MIICOL I EMAC MII collision detect
M_SSI1CLK I/O SSI-1 clock
C_EPWM8A O Enhanced PWM-8 output A
PJ5_GPIO61 56 I/O/Z General-purpose input/output 61 PU 6 mA
M_EPI0S29 I/O EPI-0 signal 29
M_CCP2 I/O Capture/Compare/PWM-2
(General-purpose Timer)
M_MIICRS I EMAC MII carrier sense
M_SSI1FSS I/O SSI-1 frame
C_EPWM8B O Enhanced PWM-8 output B
PJ6_GPIO62 53 I/O/Z General-purpose input/output 62 PU 6 mA
M_EPI0S30 I/O EPI-0 signal 30
M_CCP1 I/O Capture/Compare/PWM-1
(General-purpose Timer)
M_MIIPHYINTR I EMAC PHY MII interrupt
M_U2RX I UART-2 receive data
C_EPWM9A O Enhanced PWM-9 output A
PJ7_GPIO63 97 I/O/Z General-purpose input/output 63 PU 4 mA
M_CCP0 I/O Capture/Compare/PWM-0
(General-purpose Timer)
M_MIIPHYRST O EMAC PHY MII reset
M_U2TX O UART-2 transmit data
C_EPWM9B O Enhanced PWM-9 output B
PC0_GPIO64 No Pin No Pin General-purpose input/output 64 is not pinned out.
PC1_GPIO65 No Pin No Pin General-purpose input/output 65 is not pinned out.
PC2_GPIO66 No Pin No Pin General-purpose input/output 66 is not pinned out.
PC3_GPIO67 No Pin No Pin General-purpose input/output 67 is not pinned out.
PC4_GPIO68 37 I/O/Z General-purpose input/output 68 PU 4 mA
M_CCP5 I Capture/Compare/PWM-5
(General-purpose Timer)
M_MIITXD3 O EMAC MII transmit data 3
M_CCP2 I Capture/Compare/PWM-2
(General-purpose Timer)
M_CCP4 I Capture/Compare/PWM-4
(General-purpose Timer)
M_EPI0S2 I/O EPI-0 signal 2
M_CCP1 I Capture/Compare/PWM-1
(General-purpose Timer)
PC5_GPIO69 38 I/O/Z General-purpose input/output 69 PU 4 mA
M_CCP1 I Capture/Compare/PWM-1
(General-purpose Timer)
M_CCP3 I Capture/Compare/PWM-3
(General-purpose Timer)
M_USB0EPEN O USB-0 external power enable
(optionally used in the host mode)
M_EPI0S3 I/O EPI-0 signal 3
PC6_GPIO70 39 I/O/Z General-purpose input/output 70 PU 4 mA
M_CCP3 I Capture/Compare/PWM-3
(General-purpose Timer)
M_U1RX I UART-1 receive data
M_CCP0 I Capture/Compare/PWM-0
(General-purpose Timer)
M_USB0PFLT I USB-0 external power error state
(optionally used in the host mode)
M_EPI0S4 I/O EPI-0 signal 4
PC7_GPIO71 40 I/O/Z General-purpose input/output 71 PU 4 mA
M_CCP4 I Capture/Compare/PWM-4
(General-purpose Timer)
M_CCP0 I Capture/Compare/PWM-0
(General-purpose Timer)
M_U1TX O UART-1 transmit data
M_USB0PFLT I USB-0 external power error state
(optionally used in the host mode)
M_EPI0S5 I/O EPI-0 signal 5
Resets
XRS 4 I/OD Digital Subsystem Reset (in) and Watchdog/Power-on Reset (out). In most applications, TI recommends that the XRS pin be tied with the ARS pin. The Digital Subsystem has a built-in POR circuit, and during a power-on condition, this pin is driven low by the Digital Subsystem. This pin is also driven low by the Digital Subsystem when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. If needed, an external circuitry may also drive this pin to assert device reset. In this case, this pin should be driven by an open-drain device. A noise filtering circuit can be connected to this pin. A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. If a capacitor is placed between XRS and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. Regardless of the source, a device reset causes the Digital Subsystem to terminate execution. The Cortex-M3 program counter points to the address contained at the location 0x00000004. The C28 program counter points to the address contained at the location 0x3FFFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an open-drain with an internal pullup. PU 4 mA
ARS 144 I/OD Analog Subsystem Reset (in) and Power-on Reset (out). TI recommends that the ARS pin be tied with the XRS pin. The Analog Subsystem has a built-in POR circuit, and during a power-on condition, this pin is driven low by the Analog Subsystem. If needed, an external circuitry may also drive this pin to assert a device reset. In this case, TI recommends that this pin be driven by an open-drain device. Regardless of the source, the Analog Subsystem reset causes the digital logic associated with the Analog Subsystem, to enter reset state. The output buffer of this pin is an open-drain with an internal pullup. PU 4 mA
Clocks
X1 93 I External oscillator input or on-chip crystal-oscillator input. To use the on-chip oscillator, a quartz crystal or a ceramic resonator must be connected across X1 and X2. See Figure 8-7.
X2 95 O On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected across X1 and X2. If X2 is not used, it must be left unconnected. See Figure 8-7.
VSSOSC 94 Clock Oscillator Ground Pin. Use this pin to connect the GND of external crystal load capacitors or the ground pin of 3-terminal ceramic resonators with built-in capacitors. Do not connect to board ground. See Figure 8-7.
XCLKIN see PJ7_GPIO63 I External oscillator input. This pin feeds a clock from an external 3.3-V oscillator to internal USB PLL module and to the CAN peripherals.
XCLKOUT see PF2_GPIO34 O/Z External oscillator output. This pin outputs a clock divided-down from the internal PLL System Clock. The divide ratio is defined in the XPLLCLKCFG register.
Boot Pins
Bmode_pin1 see PG3_GPIO43 I One of four boot mode pins. Bmode_pin1 selects a specific configuration source from which the Concerto device boots on start-up. PU
Bmode_pin2 see PG7_GPIO47 I One of four boot mode pins. Bmode_pin2 selects a specific configuration source from which the Concerto device boots on start-up. PU
Bmode_pin3 see PF3_GPIO35 I One of four boot mode pins. Bmode_pin3 selects a specific configuration source from which the Concerto device boots on start-up. PU
Bmode_pin4 see PF2_GPIO34 I One of four boot mode pins. Bmode_pin4 selects a specific configuration source from which the Concerto device boots on start-up. PU
JTAG
TRST 85 I JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE:TRST is an active-low test pin and must be maintained low during normal device operation. An external pulldown resistor is required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Because the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debugger and the application. PD
TCK 89 I JTAG test clock
TMS 87 I JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. PU
TDI 88 I JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. PU
TDO 84 O JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. 4 mA
EMU0 83 I/O/Z Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the JTAG debug probe system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is required on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Because the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debugger and the application.
NOTE: If EMU0 is 0 and EMU1 is 1 when coming out of reset, the device enters Wait-in-Reset mode. WIR suspends bootloader execution, allowing the JTAG debug probe to connect to the device and to modify FLASH contents.		 PU 4 mA
EMU1 86 I/O/Z Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the JTAG debug probe system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is required on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Because the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debugger and the application.
NOTE: If EMU0 is 0 and EMU1 is 1 when coming out of reset, the device enters Wait-in-Reset mode. WIR suspends bootloader execution, allowing the JTAG debug probe to connect to the device and to modify FLASH contents.		 PU 4 mA
ITM Trace (Arm Instrumentation Trace Macrocell)
TRACED0 see PF3_GPIO35 O ITM Trace data 0 4 mA
TRACED1 see PG3_GPIO43 O ITM Trace data 1 4 mA
TRACED2 see PF0_GPIO32 O ITM Trace data 2 4 mA
TRACED3 see PF1_GPIO33 O ITM Trace data 3 4 mA
TRACECLK see PF2_GPIO34 O ITM Trace clock 4 mA
Test Pins
FLT1 16 I/O FLASH Test Pin 1. Reserved for TI. Must be left unconnected.
FLT2 21 I/O FLASH Test Pin 2. Reserved for TI. Must be left unconnected.
Internal Voltage Regulator Control
VREG18EN 113 Internal 1.8-V VREG Enable/Disable for VDD18. Pull low to enable the internal 1.8-V voltage regulator (VREG18), pull high to disable VREG18. PD
VREG12EN 101 Internal 1.2-V VREG Enable/Disable for VDD12. Pull low to enable the internal 1.2-V voltage regulator (VREG12), pull high to disable VREG12. PD
Digital Logic Power Pins for I/Os, Flash, USB, and Internal Oscillators
VDDIO 107 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. When the 1.2-V VREG is enabled (by pulling the VREG12EN pin low), these pins also supply power to the Digital Subsystem. When the 1.8-V VREG is enabled (by pulling the VREG18EN pin low), these pins also supply power to the Analog Subsystem.
VDDIO 10
VDDIO 25
VDDIO 34
VDDIO 44
VDDIO 54
VDDIO 59
VDDIO 105
VDDIO 3
VDDIO 67
VDDIO 74
VDDIO 92
VDDIO 100
VDDIO 96
VDDIO 17
VDDIO 2
VDDIO 106
Digital Logic Power Pins (Analog Subsystem)
VDD18 1 1.8-V Digital Logic Power Pins (associated with the Analog Subsystem) - no supply needed when using internal VREG18. Tie with 1.2-µF (minimum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used but could impact supply-rail ramp-up time.
VDD18 108
Digital Logic Power Pins (Master and Control Subsystems)
VDD12 24 1.2-V Digital Logic Power Pins - no supply needed when using internal VREG12. Tie with 250-nF (minimum) to 750-nF (maximum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used but could impact supply-rail ramp-up time.
VDD12 55
VDD12 66
VDD12 99
VDD12 75
VDD12 58
VDD12 11
VDD12 90
Digital Logic Ground (Analog, Master, and Control Subsystems)
VSS PWR PAD Digital Ground Power Pad (located on the bottom of the chip)
No Connect Pins
NC 91 This pin is a "no connect" (that is, this pin is not connected to any circuitry internal to the device).
(1) Throughout this table, Master Subsystem signals are denoted by the color blue; Control Subsystem signals are denoted by the color green; and Analog Subsystem signals are denoted by the color orange.
(2) I = Input, O = Output, Z = High Impedance, OD = Open Drain
(3) PU = Pullup, PD = Pulldown
  • GPIO_MUX1 pullups can be enabled or disabled by Cortex-M3 software (disabled on reset).
  • GPIO_MUX2 pullups can be enabled or disabled by C28x software (disabled on reset).
  • AIO_MUX1 and AIO_MUX2 terminals do not have pullups or pulldowns.
  • All other pullups are always enabled ( XRS, ARS, TMS, TDI, EMU0, EMU1).
  • All pulldowns are always enabled ( VREG18EN, VREG12EN, TRST).
(4) All I/Os, except for GPIO135, are glitch-free during power up and power down. See Section 8.11.
(5) This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices.
(6) Output from the Concerto ePWM is meant for the external ADC (if present).