JAJSQA0D
december 2011 – december 2020
HD3SS212
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Function
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Parameter Measurement Information
7.1
Test Timing Diagrams
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.1.1
AC Coupling Caps
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Receiving Notification of Documentation Updates
11.2
Community Resource
11.3
Trademarks
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
ZXH|48
MPBGAS3
サーマルパッド・メカニカル・データ
発注情報
jajsqa0d_oa
jajsqa0d_pm
9.2.2
Detailed Design Procedure
Connect VDD and GND pins to the power and ground planes of the printed circuit board, with 0.1-µF bypass capacitor
Use +3.3-V TTL/CMOS logic level at SEL
Use controlled-impedance transmission media for all the differential signals
Ensure the received complimentary signals are with a differential amplitude of < 1800 mVpp and a common-mode voltage of < 2V.