JAJSRJ2A September   2000  – January 2024 INA114

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Setting the Gain
      2. 6.1.2 Noise Performance
      3. 6.1.3 Offset Trimming
      4. 6.1.4 Input Bias Current Return Path
      5. 6.1.5 Input Common-Mode Range
      6. 6.1.6 Input Protection
      7. 6.1.7 Output Voltage Sense (SOIC-16 Package Only)
  8. Typical Applications
  9. Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • P|8
  • DW|16
サーマルパッド・メカニカル・データ
発注情報

Input Bias Current Return Path

The input impedance of the INA114 is extremely high-approximately 1010Ω. However, a path must be provided for the input bias current of both inputs. This input bias current is typically less than ±1nA, and can be either polarity as a result of cancellation circuitry. High input impedance means that this input bias current changes very little with varying input voltage.

Input circuitry must provide a path for this input bias current if the INA114 is to operate properly. Figure 6-3 shows various provisions for an input bias current path. Without a bias current return path, the inputs float to a potential that exceeds the common-mode range of the INA114 and the input amplifiers saturate. If the differential source resistance is low, the bias current return path can be connected to one input (see thermocouple example in Figure 6-3). With higher source impedance, use two resistors to provide a balanced input, with the possible advantages of lower input offset voltage due to bias current and better common-mode rejection.

GUID-78C13D33-82C0-435F-9FEE-47BF15B487A5-low.png Figure 6-3 Providing an Input Common-Mode Current Path.