JAJSQM9A September   2000  – August 2023 INA141

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Revision History
  6. 5Pin Configuration and Functions
  7. 6Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Setting the Gain
      2. 7.1.2 Dynamic Performance
      3. 7.1.3 Noise Performance
      4. 7.1.4 Offset Trimming
      5. 7.1.5 Input Bias Current Return Path
      6. 7.1.6 Input Common-Mode Range
      7. 7.1.7 Low-Voltage Operation
      8. 7.1.8 Input Protection
  9. 8Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, VCM = VS / 2, and G = 10 V/V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VOS Offset voltage (RTI)  INA141P, INA141U G = 10 V/V ±50 ±100 µV
G = 100 V/V ±20 ±50

INA141PA, INA141UA

 G = 10 V/V ±50 ±250
G = 100 V/V ±20 ±125
Offset voltage drift (RTI) TA = –40°C to +85°C INA141P, 
INA141U		 G = 10 V/V ±0.5 ±2 µV/℃
G = 100 V/V ±0.2 ±0.5
INA141PA, 
INA141UA		 G = 10 V/V ±0.5 ±2.5
G = 100 V/V ±0.2 ±1.5
PSRR Power-supply rejection ratio (RTI) VS = ±2.25 V to ±18 V INA141P, 
INA141U		 G = 10 V/V ±2 ±10 µV/V
G = 100 V/V ±0.4 ±1
INA141PA, 
INA141UA		 G = 10 V/V ±2 ±20
G = 100 V/V ±0.4 ±3
Long-term stability G = 10 V/V 0.5 µV/mo
G = 100 V/V 0.2 µV/mo
Input impedance Differential 100 || 2 GΩ || pF
Common-mode 100 || 9
VCM Common-mode voltage(1) VO = 0 V (V–) +2 (V+) – 2 V
CMRR Common-mode rejection 
VCM = ±13 V,
ΔRS = 1 kΩ
 		 INA141P, 
INA141U		 G = 10 V/V 100 106 dB
G = 100 V/V 117 125
INA141PA, 
INA141UA		 G = 10 V/V 93 100
G = 100 V/V 110 120
INPUT BIAS CURRENT
IB Input bias current INA141P, INA141U ±2 ±5 nA
INA141PA, INA141UA
±2

 ±10
Input bias current drift  TA = –40°C to +85°C ±30 pA/℃
IOS Input offset current INA141P, INA141U ±1 ±5 nA
INA141PA, INA141UA ±1 ±10 nA
Input offset current drift  TA = –40°C to +85°C ±30 pA/℃
NOISE
eN Voltage noise (RTI) RS = 0 Ω G = 10 V/V f = 10 Hz 22 nV/√Hz
f = 100 Hz 13
f = 1 kHz 12
fB = 0.1 Hz to 10 Hz 0.6 µVPP
G = 100 V/V f = 10 Hz 10 nV/√Hz
f = 100 Hz 8
f = 1 kHz 8
fB = 0.1 Hz to 10 Hz 0.2 µVPP
In Current noise f = 10 Hz 0.9 pA/√Hz
f = 1 kHz 0.3
fB = 0.1 Hz to 10 Hz 30 pAPP
GAIN
G Gain 10 100 V/V
GE Gain error VO = ±13.6 V INA141P, INA141U G = 10 V/V ±0.01 ±0.05 %
G = 100 V/V ±0.03 ±0.075
INA141PA, INA141UA G = 10 V/V ±0.01 ±0.15
G = 100 V/V ±0.03 ±0.15
Gain drift(6) G = 10 V/V or 100 V/V, TA = –40°C to +85°C  ±2 ±10 ppm/°C
Gain nonlinearity INA141P, INA141U G = 10 V/V ±0.0003 ±0.001 % of FSR
G = 100 V/V ±0.0005 ±0.002
INA141PA, INA141UA G = 10 V/V ±0.0003 ±0.002
G = 100 V/V ±0.0005 ±0.004
OUTPUT
Output voltage (V–) + 1.4 (V±) ∓ 0.9 (V+) – 1.4 V
CL Load capacitance Stable operation 1000 pF
ISC Short-circuit current Continuous to VS / 2 ±20 mA
FREQUENCY RESPONSE
BW Bandwidth, –3 dB G = 10 V/V 610 kHz
G = 100 V/V 200 kHz
SR Slew rate G = 10 V/V, VO = ±10 V 2 V/µs
tS Settling time To 0.01%, VO = ±5 V G = 10 V/V 7 µs
G = 100 V/V 9
Overload recovery 50% input overload 4 µs
POWER SUPPLY
IQ Quiescent current VIN = 0 V ±750 ±800 µA
(1) Input common-mode voltage varies with output voltage; see Typical Characteristics.
(2) Specified by wafer test.