JAJSCS8B December   2016  – November 2018 INA1650 , INA1651

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     INA165xの簡略化された内部回路図
  3. 3 概要
    1.     CMRRヒストグラム(5746チャネル)
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics:
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Audio Signal Path
      2. 7.3.2 Supply Divider
      3. 7.3.3 Electrical Overstress
      4. 7.3.4 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Single-Supply Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Common-Mode Range
      2. 8.1.2 Common-Mode Input Impedance
      3. 8.1.3 Start-Up Time in Single-Supply Applications
      4. 8.1.4 Input AC Coupling
      5. 8.1.5 Supply Divider Capacitive Loading
    2. 8.2 Typical Applications
      1. 8.2.1 Line Receiver for Differential Audio Signals in a Split-Supply System
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Differential Line Receiver for Single-Supply Applications
      3. 8.2.3 Floating Single-Ended Input Line Receiver for Ground Loop Noise Reduction
      4. 8.2.4 Floating Single-Ended Input Line Receiver With Differential Outputs
      5. 8.2.5 TRS Audio Interface in Single-Supply Applications
      6. 8.2.6 Differential Line Driver With Single-Ended Input
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 TINA-TI(無料のダウンロード・ソフトウェア)
        2. 11.1.1.2 TI Precision Designs
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 関連リンク
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 コミュニティ・リソース
    6. 11.6 商標
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics:

at TA = 25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = midsupply, and RL = 2 kΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO PERFORMANCE
THD+N Total harmonic distortion + noise VO = 3 VRMS, f = 1kHz, 90-kHz measurement bandwidth, VS = ±18 V 0.00039%
–108.1 dB
VIN = 22 dBu (9.7516 VRMS) , FIN = 1 kHz, VS = ±18 V,
90-kHz measurement bandwidth		 0.000174%
–115.2 dB
IMD Intermodulation distortion SMPTE and DIN two-tone, 4:1 (60 Hz and 7 kHz)
VO = 3 VRMS, 90-kHz measurement bandwidth		 0.0005%
–106.1 dB
CCIF twin-tone (19 kHz and 20 kHz),
VO = 3 VRMS, 90-kHz measurement bandwidth		 0.00066%
–103.6 dB
AC PERFORMANCE
BW Small-signal bandwidth 2.7 MHz
SR Slew rate 10 V/μs
Full-power bandwidth(1) VO = 1 VP 1.59 MHz
PM Phase margin CL = 20 pF 71°
CL = 200 pF 54°
ts Settling time To 0.01%, Vs = ±18 V, 10-V step 2.2 μs
Overload recovery time 330 ns
Channel separation f = 1 kHz, REF and COM pins connected to ground 140 dB
f = 1 kHz, REF and COM pins connected to VMID(OUT) 130 dB
EMI/RFI filter corner frequency 80 MHz
NOISE
Output voltage noise f = 20 Hz to 20 kHz, no weighting 4.5 μVRMS
–104.7 dBu
en Output voltage noise density(2) f = 100 Hz 47 nV/√Hz
f = 1 kHz 31
OFFSET VOLTAGE
VOS Output offset voltage ±1 ±3 mV
TA = –40°C to +125°C(2) ±4
dVOS/dT Output offset voltage drift(2) TA = –40°C to +125°C 2 7 μV/°C
PSRR Power-supply rejection ratio 2 μV/V
GAIN
Gain 1 V/V
Gain error 0.04% 0.05%
TA = –40°C to +125°C(2) 0.05% 0.06%
Gain nonlinearity VS = ±18 V, –10 V < VO < 10 V (2) 1 5 ppm
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) + 0.25 (V+) – 2 V
CMRR Common-mode rejection ratio (V–) + 0.25 V ≤ VCM ≤ (V+) – 2 V, REF and COM pins connected to ground, VS = ±18 V 85 91 dB
TA = –40°C to +125°C(2) 82 89
(V–) + 0.25 V ≤ VCM ≤ (V+) – 2 V, REF and COM pins connected to VMID(OUT), VS = ±18 V 82 86
TA = –40°C to +125°C(2) 76 84
CMRR Common-mode rejection ratio (V–) + 0.25 V ≤ VCM ≤ (V+) – 2 V, REF and COM pins connected to ground, VS = ±18 V, RS mismatch = 20 Ω 84 dB
INPUT IMPEDANCE
Differential 850 1000 1150 kΩ
Common-mode 212.5 250 287.5 kΩ
Input resistance mismatch 0.01% 0.25%
SUPPLY DIVIDER CIRCUIT
Nominal output voltage [ (V+) + (V–) ] / 2 V
Output voltage offset VMID(IN) = ((V+) + (V–) / 2 2 4 mV
Input impedance VMID(IN) pin, f = 1 kHz 250 kΩ
Output resistance VMID(OUT) pin 0.35 Ω
Output voltage noise 20 Hz to 20 kHz, CMID = 1 µF 1.56 µVRMS
Output capacitive load limit Phase margin > 45°, RISO = 0 Ω 150 pF
OUTPUT
VO Voltage output swing from rail Positive rail RL = 2 kΩ 350 mV
RL = 600 Ω 1100
Negative rail RL = 2 kΩ 430
RL = 600 Ω 1300
ZOUT Output impedance f ≤ 100 kHz, IOUT = 0 A < 1 Ω
ISC Short-circuit current VS = ±18 V ±75 mA
CLOAD Capacitive load drive See Figure 19 pF
POWER SUPPLY
IQ Quiescent current IOUT = 0 A, INA1651 4.6 6 6.9 mA
TA = –40°C to +125°C(2) 8
IOUT = 0 A, INA1650 8 10.5 12
TA = –40°C to +125°C(2) 14
(1) Full-power bandwidth = SR / (2π × VP), where SR = slew rate.
(2) Specified by design and characterization.