JAJSIZ8B July   2015  – September 2024 INA226-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Basic ADC Functions
        1. 6.3.1.1 Power Calculation
        2. 6.3.1.2 Alert Pin
    4. 6.4 Device Functional Modes
      1. 6.4.1 Averaging and Conversion Time Considerations
      2. 6.4.2 Filtering and Input Considerations
    5. 6.5 Programming
      1. 6.5.1 Programming the Calibration Register
      2. 6.5.2 Programming the Power Measurement Engine
        1. 6.5.2.1 Calibration Register and Scaling
      3. 6.5.3 Simple Current Shunt Monitor Usage (No Programming Necessary)
      4. 6.5.4 Default Settings
      5. 6.5.5 Bus Overview
        1. 6.5.5.1 Serial Bus Address
        2. 6.5.5.2 Serial Interface
        3. 6.5.5.3 Writing to and Reading From the INA226-Q1
          1. 6.5.5.3.1 High-Speed I2C Mode
        4. 6.5.5.4 SMBus Alert Response
  8. 7 Registers
    1. 7.1 Register Maps
      1. 7.1.1  Configuration Register (00h) (Read/Write)
      2. 7.1.2  Shunt Voltage Register (01h) (Read-Only)
      3. 7.1.3  Bus Voltage Register (02h) (Read-Only) #GUID-792F23A7-1E45-4FB9-9334-0BF769622DE4/SBOS5477597
      4. 7.1.4  Power Register (03h) (Read-Only)
      5. 7.1.5  Current Register (04h) (Read-Only)
      6. 7.1.6  Calibration Register (05h) (Read/Write)
      7. 7.1.7  Mask/Enable Register (06h) (Read/Write)
      8. 7.1.8  Alert Limit Register (07h) (Read/Write)
      9. 7.1.9  Manufacturer ID Register (FEh) (Read-Only)
      10. 7.1.10 Die ID Register (FFh) (Read-Only)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 High-Side Sensing Circuit Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1.7 Mask/Enable Register (06h) (Read/Write)

The Mask/Enable Register selects the function that is enabled to control the Alert pin as well as how that pin functions. If multiple functions are enabled, the highest significant bit position Alert Function (D15-D11) takes priority and responds to the Alert Limit Register.

Table 7-12 Mask/Enable Register (06h) (Read/Write)
BIT #D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
BIT
NAME		SOLSULBOLBULPOLCNVR—————AFFCVRFOVFAPOLLEN
POR VALUE0000000000000000
SOL:Shunt Voltage Over-Voltage
Bit 15Setting this bit high configures the Alert pin to be asserted if the shunt voltage measurement following a conversion exceeds the value programmed in the Alert Limit Register.
SUL:Shunt Voltage Under-Voltage
Bit 14Setting this bit high configures the Alert pin to be asserted if the shunt voltage measurement following a conversion drops below the value programmed in the Alert Limit Register.
BOL:Bus Voltage Over-Voltage
Bit 13Setting this bit high configures the Alert pin to be asserted if the bus voltage measurement following a conversion exceeds the value programmed in the Alert Limit Register.
BUL:Bus Voltage Under-Voltage
Bit 12Setting this bit high configures the Alert pin to be asserted if the bus voltage measurement following a conversion drops below the value programmed in the Alert Limit Register.
POL:Power Over-Limit
Bit 11Setting this bit high configures the Alert pin to be asserted if the Power calculation made following a bus voltage measurement exceeds the value programmed in the Alert Limit Register.
CNVR:Conversion Ready
Bit 10Setting this bit high configures the Alert pin to be asserted when the Conversion Ready Flag, Bit 3, is asserted indicating that the device is ready for the next conversion.
AFF:Alert Function Flag
Bit 4While only one Alert Function can be monitored at the Alert pin at a time, the Conversion Ready can also be enabled to assert the Alert pin. Reading the Alert Function Flag following an alert allows the user to determine if the Alert Function is the source of the Alert.

When the Alert Latch Enable bit is set to Latch mode, the Alert Function Flag bit clears only when the Mask/Enable Register is read. When the Alert Latch Enable bit is set to Transparent mode, the Alert Function Flag bit is cleared following the next conversion that does not result in an Alert condition.

CVRF:Conversion Ready Flag
Bit 3Although the device can be read at any time, and the data from the last conversion is available, the Conversion Ready Flag bit is provided to help coordinate one-shot or triggered conversions. The Conversion Ready Flag bit is set after all conversions, averaging, and multiplications are complete. Conversion Ready Flag bit clears under the following conditions:

1.) Writing to the Configuration Register (except for Power-Down selection)

2.) Reading the Mask/Enable Register

OVF:Math Overflow Flag
Bit 2This bit is set to '1' if an arithmetic operation resulted in an overflow error. The bit indicates that current and power data can be invalid.
APOL:Alert Polarity bit; sets the Alert pin polarity.
Bit 11 = Inverted (active-high open collector)
0 = Normal (active-low open collector) (default)
LEN:Alert Latch Enable; configures the latching feature of the Alert pin and Alert Flag bits.
Bit 01 = Latch enabled
0 = Transparent (default)

When the Alert Latch Enable bit is set to Transparent mode, the Alert pin and Flag bit resets to the idle states when the fault has been cleared. When the Alert Latch Enable bit is set to Latch mode, the Alert pin and Alert Flag bit remains active following a fault until the Mask/Enable Register has been read.