デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
INA231 は1.8V I2C 準拠 インターフェイス付きの電流シャント/電力モニタで、16 個のプログラマブル・アドレスを備えています。INA231 はシャント電圧降下とバス電源電圧の両方を監視し、その値がプログラムされた範囲を外れたときは ALERTピンをアサートして、保護を強化します。較正値、変換時間、平均化オプションをプログラム可能で、内蔵のマルチプライヤと組み合わせて電流のアンペア値や電力のワット値を直接読み出すことができ、ホストの処理が軽減されます。
INA231 は 0V~28V のバス電圧上で電流を検出します。デバイスは単一の 2.7V~5.5V 電源で動作し、消費電流は 330μA (標準値) です。INA231 は、-40℃~+125℃ の温度範囲で動作が規定されています。
INA231 には2つのバージョンがあり、INA231A はスタートアップ時からシャントおよびバス電圧の連続変換を実行し、INA231B は低消費電流のパワー・ダウン・モードでスタートアップします。
部品番号 | パッケージ | 本体サイズ (公称) |
---|---|---|
INA231A | YFF (DSBGA-12) | 1.65mm × 1.39mm × 0.62mm |
YFD (DSBGA-12) | 1.65mm × 1.39mm × 0.40mm | |
INA231B | YFD (DSBGA-12) | 1.65mm × 1.39mm × 0.40mm |
Changes from Revision C (March 2018) to Revision D (July 2022)
Changes from Revision B (August 2017) to Revision C (March 2018)
Changes from Revision A (June 2017) to Revision B (August 2017)
Changes from Revision * (February 2013) to Revision A (June 2017)
DEVICE | DESCRIPTION |
---|---|
INA209 | Current and power monitor with watchdog, peak-hold, and fast comparator functions |
INA210, INA211, INA212, INA213, INA214, INA215 | Zerø-drift, low-cost, analog current shunt monitor series in small package |
INA219 | Zerø-drift, bidirectional current power monitor with two-wire interface |
INA226 | High or Low-side, bidirectional current and power monitor with two-wire interface and programmable alert |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
A0 | B3 | Digital input | Address pin. Connect to GND, SCL, SDA, or VS. Table 8-2 shows pin settings and corresponding addresses. |
A1 | C3 | Digital input | Address pin. Connect to GND, SCL, SDA, or VS. Table 8-2 shows pin settings and corresponding addresses. |
ALERT | A3 | Digital output | Multi-functional alert, open-drain output. |
GND | C1 | Analog | Ground |
NC | B2, C2(1) | — | Do not connect, leave floating. |
SCL | A1 | Digital input | Serial bus clock line, open-drain input. |
SDA | A2 | Digital input/output | Serial bus data line, open-drain input/output. |
BUS | D1 | Analog input | Bus voltage input. |
IN– | D2 | Analog input | Negative differential shunt voltage input. Connect to load side of shunt resistor. |
IN+ | D3 | Analog input | Positive differential shunt voltage input. Connect to supply side of shunt resistor. |
VS | B1 | Analog | Power supply pin, 2.7 V to 5.5 V. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage, VS | 6 | V | ||
Analog inputs, IN+, IN– | Differential (VIN+) – (VIN–)(2) | –30 | 30 | V |
Common-mode | –0.3 | 30 | V | |
SDA | GND – 0.3 | 6 | V | |
SCL | GND – 0.3 | 6 | V | |
Input current into any pin | 5 | mA | ||
Open-drain digital output current | 10 | mA | ||
Operating ambient temperature, TA | –40 | 125 | °C | |
Junction temperature, TJ | 150 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | 2500 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | 1000 | |||
Machine model (MM) | 150 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VCM | Common-mode voltage | 0 | 28 | V | |
VS | Operating supply voltage | 2.7 | 5.5 | V | |
TA | Operating ambient temperature | –40 | 125 | °C |
THERMAL METRIC(1) | INA231 | UNIT | ||
---|---|---|---|---|
YFD (DSBGA) | YFF (DSBGA) | |||
12 PINS | 12 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 83.8 | 90.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 0.4 | 0.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 19.3 | 40.0 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.3 | 3.0 | °C/W |
ψJB | Junction-to-board characterization parameter | 19.4 | 39.2 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SHUNT INPUT | ||||||
Shunt voltage input | –81.92 | 81.9175 | mV | |||
CMR | Common-mode rejection | VIN+ = 0 V to 28 V | 100 | 120 | dB | |
VOS | Shunt offset voltage, RTI(1) | ±10 | ±50 | μV | ||
TA = –40°C to +125°C | 0.1 | 0.5 | μV/°C | |||
PSRR | vs power supply | VS = 2.7 V to 5.5 V | 10 | μV/V | ||
BUS INPUT | ||||||
Bus voltage input range(2) | 0 | 28 | V | |||
VOS | Bus offset voltage, RTI(1) | ±5 | ±30 | mV | ||
TA = –40°C to +125°C | 10 | 40 | μV/°C | |||
PSRR | vs power supply | 2 | mV/V | |||
BUS pin input impedance | 830 | kΩ | ||||
INPUT | ||||||
IIN+, IIN- | Input bias current | 10 | μA | |||
Input leakage(3) | (VIN+) + (VIN–), Power-Down mode | 0.1 | 0.5 | μA | ||
DC ACCURACY | ||||||
ADC native resolution | 16 | Bits | ||||
1 LSB step size | Shunt voltage | 2.5 | μV | |||
Bus voltage | 1.25 | mV | ||||
Shunt voltage gain error | 0.2% | 0.5% | ||||
TA = –40°C to +125°C | 10 | 50 | ppm/°C | |||
Bus voltage gain error | 0.2% | 0.5% | ||||
TA = –40°C to +125°C | 10 | 50 | ppm/°C | |||
Differential nonlinearity | ±0.1 | LSB | ||||
ADC conversion time | CT bit = 000 | 140 | 154 | μs | ||
CT bit = 001 | 204 | 224 | μs | |||
CT bit = 010 | 332 | 365 | μs | |||
CT bit = 011 | 588 | 646 | μs | |||
CT bit = 100 | 1.1 | 1.21 | ms | |||
CT bit = 101 | 2.116 | 2.328 | ms | |||
CT bit = 110 | 4.156 | 4.572 | ms | |||
CT bit = 111 | 8.244 | 9.068 | ms | |||
SMBus | ||||||
SMBus timeout(4) | 28 | 35 | ms | |||
DIGITAL INPUT/OUTPUT | ||||||
Input capacitance | 3 | pF | ||||
Leakage input current | 0 ≤ VIN ≤ VS | 0.5 | 2 | μA | ||
VIH | High-level input voltage | 1.4 | 6 | V | ||
VIL | Low-level input voltage | –0.5 | 0.4 | V | ||
VOL | Low-level output voltage (SDA, ALERT) | IOL = 3 mA | 0 | 0.4 | V | |
Hysteresis | 500 | mV | ||||
POWER SUPPLY | ||||||
Quiescent current | 330 | 420 | μA | |||
Power-Down mode | 3 | 7 | μA | |||
Power-on reset threshold | 2 | V |
FAST MODE | HIGH-SPEED MODE | UNIT | |||||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||
f(SCL) | SCL operating frequency | INA231A | 0.001 | 0.4 | 0.001 | 2.5 | MHz | ||
INA231B | 0.01 | 0.4 | 0.01 | 2.5 | |||||
t(BUF) | Bus free time between stop and start conditions | 600 | 260 | ns | |||||
t(HDSTA) | Hold time after repeated START condition. After this period, the first clock is generated. | 100 | 100 | ns | |||||
t(SUSTA) | Repeated start condition setup time | 100 | 100 | ns | |||||
t(SUSTO) | STOP condition setup time | 100 | 100 | ns | |||||
t(HDDAT) | Data hold time, VS ≤ 3.3 V | 0 | 0 | 130 | ns | ||||
t(HDDAT) | Data hold time, VS > 3.3 V | 10 | 10 | 130 | ns | ||||
t(SUDAT) | Data setup time | 100 | 50 | ns | |||||
t(LOW) | SCL clock low period | 1300 | 260 | ns | |||||
t(HIGH) | SCL clock high period | 600 | 60 | ns | |||||
tF | Data fall time | 300 | 80 | ns | |||||
tR | Data rise time | 300 | 80 | ns | |||||
tF | Clock fall time | 300 | 40 | ns | |||||
tR | Clock rise time | 300 | 40 | ns | |||||
tR | Clock/data rise time for SCLK ≤ 100 kHz | 1000 | ns |
at TA = 25°C, VS = 3.3 V,VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV, and VBUS = 12 V (unless otherwise noted)
Conversion time = 1.1 ms |