JAJSJ04A May   2020  – June 2021 INA239-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements (SPI)
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Versatile High Voltage Measurement Capability
      2. 7.3.2 Power Calculation
      3. 7.3.3 Low Bias Current
      4. 7.3.4 High-Precision Delta-Sigma ADC
        1. 7.3.4.1 Low Latency Digital Filter
        2. 7.3.4.2 Flexible Conversion Times and Averaging
      5. 7.3.5 Integrated Precision Oscillator
      6. 7.3.6 Multi-Alert Monitoring and Fault Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 SPI Frame
    6. 7.6 Register Maps
      1. 7.6.1 INA239-Q1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Measurement Range and Resolution
      2. 8.1.2 Current and Power Calculations
      3. 8.1.3 ADC Output Data Rate and Noise Performance
      4. 8.1.4 Input Filtering Considerations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the Shunt Resistor
        2. 8.2.2.2 Configure the Device
        3. 8.2.2.3 Program the Shunt Calibration Register
        4. 8.2.2.4 Set Desired Fault Thresholds
        5. 8.2.2.5 Calculate Returned Values
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.6 Multi-Alert Monitoring and Fault Detection

The INA239-Q1 includes a multipurpose, open-drain ALERT output pin that can be used to report multiple diagnostics or as an indicator that the ADC conversion is complete when the device is operating in both triggered and continuous conversion mode. The diagnostics listed in Table 7-1 are constantly monitored and can be reported through the ALERT pin whenever the monitored output value crosses its associated out-of-range threshold.

Table 7-1 ALERT Diagnostics Description
INA239-Q1 DIAGNOSTICSTATUS BIT IN DIAG_ALRT REGISTER (RO)OUT-OF-RANGE THRESHOLD REGISTER (R/W)REGISTER DEFAULT VALUE
Shunt Under Voltage LimitSHNTULSUVL0x8000 h
(two's complement)
Shunt Over Voltage LimitSHNTOLSOVL0x7FFF h
(two's complement)
Bus Voltage Over-LimitBUSOLBOVL0x7FFF h
(two's complement, positive values only)
Bus Voltage Under-LimitBUSULBUVL0x0000 h
(two's complement, positive values only)
Temperature Over-LimitTMPOLTEMP_LIMIT0xFFFF h
(two's complement, positive values only)
Power Over-LimitPOLPWR_LIMIT0x7FFF h
(two's complement)

A read of the DIAG_ALRT register is used to determine which diagnostic has triggered the ALERT pin. This register, shown in Table 7-13, is also used to monitor other associated diagnostics as well as configure some ALERT pin functions.

  • Alert latch enable — In case the ALERT pin is triggered, this function will hold the value of the pin even after all diagnostic conditions have cleared. A read of the DIAG_ALRT register will reset the status of the ALERT pin. This function is enabled by setting the ALATCH bit.
  • Conversion ready enable — Enables the ALERT pin to assert when an ADC conversion has completed and output values are ready to be read through the digital interface. This function is enabled by setting the CNVR bit. The conversion completed events can also be read through the CNVRF bit regardless of the CNVR bit setting.
  • Alert comparison on averaged output — Allows the out-of-range threshold value to be compared to the averaged data values produced by the ADC. This helps to additionally remove noise from the output data when compared to the out-of-range threshold to avoid false alerts due to noise. However, the diagnostic will be delayed due to the time needed for averaging. This function is enabled by setting the SLOWALERT bit.
  • Alert polarity — Allows the device to invert the active state of the ALERT pin. Note that the ALERT pin is an open-drain output that must be pulled-up by a resistor. The ALERT pin is active-low by default and can be configured for active high function using the APOL control bit.

Other diagnostic functions that are not reported by the ALERT pin but are available by reading the DIAG_ALRT register:

  • Math overflow — Indicated by the MATHOF bit, reports when an arithmetic operation has caused an internal register overflow.
  • Memory status — Indicated by the MEMSTAT bit, monitors the health of the device non-volatile trim memory. This bit should always read '1' when the device is operating properly.

When the ALERT pin is configured to report the ADC conversion complete event, the ALERT pin becomes a multipurpose reporting output. Figure 7-6 shows an example where the device reports ADC conversion complete events while the INA239-Q1 device is subject to shunt over voltage (over current) event, bus under voltage event, over temperature event and over power-limit event.

GUID-20201220-CA0I-WJ77-MWWM-GCQ7JNV0QHWG-low.gif Figure 7-6 Multi-Alert Configuration