JAJSJ04A May   2020  – June 2021 INA239-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements (SPI)
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Versatile High Voltage Measurement Capability
      2. 7.3.2 Power Calculation
      3. 7.3.3 Low Bias Current
      4. 7.3.4 High-Precision Delta-Sigma ADC
        1. 7.3.4.1 Low Latency Digital Filter
        2. 7.3.4.2 Flexible Conversion Times and Averaging
      5. 7.3.5 Integrated Precision Oscillator
      6. 7.3.6 Multi-Alert Monitoring and Fault Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 SPI Frame
    6. 7.6 Register Maps
      1. 7.6.1 INA239-Q1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Measurement Range and Resolution
      2. 8.1.2 Current and Power Calculations
      3. 8.1.3 ADC Output Data Rate and Noise Performance
      4. 8.1.4 Input Filtering Considerations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the Shunt Resistor
        2. 8.2.2.2 Configure the Device
        3. 8.2.2.3 Program the Shunt Calibration Register
        4. 8.2.2.4 Set Desired Fault Thresholds
        5. 8.2.2.5 Calculate Returned Values
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5.1.1 SPI Frame

SPI communication to the INA239-Q1 device is performed through register address access. Communication to every register starts with a 6-bit register address followed by a "0" and a R/W bit. Setting the R/W bit to "1" indicates that the current SPI frame will read from a device register while setting the R/W bit to "0" indicates the current SPI frame will write data to a device register.

GUID-20201103-CA0I-WLZZ-WZBC-PNBXZTHTVZ59-low.gifFigure 7-7 SPI Read Frame
GUID-20201103-CA0I-D8DF-BW6S-XTSRRVMWSQDN-low.gifFigure 7-8 SPI Write Frame

Note that while the read frame can be variable in length due to the different length registers in the INA239-Q1 device, the write frame is fixed in length as all writable registers are 16 bits wide. During an SPI write frame, while new data is shifted into the INA239-Q1 register, the old data from the same register is shifted out on the MISO line.

The first 8-bits of each SPI frame are presented in Table 7-2, which shows access to a certain register address on the MOSI line as well as read/write functionality. On an SPI read operation, the INA239-Q1 returns the data read in the same SPI frame.

Table 7-2 First 8-MSB Bits of SPI Frame
COMMANDb7b6b5b4b3b2b1b0
READADDR5ADDR4ADDR3ADDR2ADDR1ADDR001
WRITE0