JAJSPA2D December   2022  – November 2024 INA351

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gain-Setting
        1. 7.3.1.1 Gain Error and Drift
      2. 7.3.2 Input Common-Mode Voltage Range
      3. 7.3.3 EMI Rejection
      4. 7.3.4 Typical Specifications and Distributions
      5. 7.3.5 Electrical Overstress
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Reference Pin
      2. 8.1.2 Input Bias Current Return Path
    2. 8.2 Typical Applications
      1. 8.2.1 Resistive-Bridge Pressure Sensor
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V) at TA = 25°C, VREF = VS/2,  G = 10, RL = 10 kΩ connected to VS / 2, VCM = [(VIN+) + (VIN–)] / 2 = VS / 2, VIN = (VIN+) – (VIN–) = 0 V and VOUT = VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VOSI Offset Voltage, RTI(1) VS = 5.5 V, G = 10, 20, 30, 50 TA = 25°C ±0.2 ±1.3 mV
Offset Voltage over T, RTI(1) VS = 5.5 V, G = 10, 20, 30, 50 TA = –40°C to 125°C ±1.4 mV
Offset temp drift, RTI(2) VS = 5.5 V, G = 10, 20, 30, 50 TA = –40°C to 125°C ±0.65 µV/°C
PSRR Power-supply rejection ratio G = 10, 20, 30, 50 TA = 25°C   20 75 µV/V
ZIN-DM Differential Impedance 100 || 5 GΩ || pF
ZIN-CM Common Mode Impedance 100 || 9 GΩ || pF
VCM Input Stage Common Mode Range(3) (V–) (V+)  V
CMRR DC Common-mode rejection ratio, RTI G = 10, 20, 30, 50, VCM = (V–) + 0.1 V to (V+) – 1 V, High CMRR Region VS = 5.5 V, VREF = VS/2 86 95 dB
G = 10, 20, 30, 50, VCM = (V–) + 0.1 V to (V+) – 1 V, High CMRR Region VS = 3.3 V, VREF = VS/2 94
G = 10, 20, 30, 50, VCM = (V–) + 0.1 V to (V+) – 0.1 V VS = 5.5 V, VREF = VS/2 62 75
BIAS CURRENT
IB Input bias current VCM = VS / 2 ±0.65 pA
IOS Input offset current VCM = VS / 2 ±0.25 pA
NOISE VOLTAGE
eNI Input referred voltage noise density(5) G = 10, 20, 30, 50 f = 1 kHz 36 nV/√Hz
G = 10, 20, 30, 50 f = 10 kHz 35
ENI Input referred voltage noise(5) G = 10, fB = 0.1 Hz to 10 Hz 3.2 µVPP
in Input current noise f = 1 kHz 22 fA/√Hz
GAIN
GE Gain error(4) G = 10, VREF = VS/2 VO = (V–) + 0.1 V to (V+) – 0.1V ±0.015 ±0.10 %
G = 20, VREF = VS/2 ±0.020 ±0.10
Gain error(4) G = 30, VREF = VS/2 ±0.020 ±0.10
G = 50, VREF = VS/2 ±0.015 ±0.10
OUTPUT
VOH Positive rail headroom RL = 10 kΩ to VS/2 15 30 mV
VOL Negative rail headroom RL = 10 kΩ to VS/2 15 30 mV
CL Drive Load capacitance drive VO = 100 mV step, Overshoot < 20% 500 pF
ZO Closed-loop output impedance f = 10 kHz 51 Ω
ISC Short-circuit current VS = 5.5 V ±20 mA
FREQUENCY RESPONSE
BW Bandwidth, –3 dB G = 10 VIN = 10 mVpk-pk 100 kHz
G = 20 50
Bandwidth, –3 dB G = 30 40
G = 50 25
THD + N Total harmonic distortion + noise VS = 5.5 V, VCM = 2.75 V, VO = 1 VRMS, G = 10, RL = 100 kΩ
ƒ = 1 kHz, 80-kHz measurement BW		 0.035 %
EMIRR Electro-magnetic interference rejection ratio f = 1 GHz, VIN_EMIRR = 100 mV 96 dB
SR Slew rate VS = 5 V, VO = 2 V step, G = 10, 20, 30, 50 0.20 V/µs
tS Settling time G = 10, To 0.1%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF 14 µs
G = 10, To 0.01%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF 24
G = 20, To 0.1%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF 20
G = 20, To 0.01%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF 30
Settling time G = 30, To 0.1%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF 30
G = 30, To 0.01%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF 40
G = 50, To 0.1%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF 45
G = 50, To 0.01%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF 55
Overload recovery VIN = 1 V, G = 10 8 µs
REFERENCE BUFFER
REF - VIN Linear input voltage range VS = 5.5 V (V–) + 0.1 (V+) – 0.1 V
REF - G Reference gain to output 1 V/V
REF - GE Reference gain error(4) VS = 5.5 V ±0.015 ±0.10 %
REF - ZIN Input impedance VS = 5.5 V 100 || 5 GΩ || pF
REF - IB Reference pin bias current VS = 5.5 V ±0.65 pA
POWER SUPPLY
VS Power-supply voltage Single-supply 1.7 5.5 V
Dual-supply ±0.85 ±2.75
IQ Quiescent current VIN = 0 V 110 135 µA
TA = –40°C to 125°C 147
IQSD Quiescent current per amplifier All amplifiers disabled, SHDN = V– 0.85 1.5 µA
VIL Logic low threshold voltage (Gain Select) G = 10 for INA351ABS, G = 30 for INA351CDS (V–) + 0.2 V V
VIH Logic high threshold voltage (Gain Select) G = 20 for INA351ABS, G = 50 for INA351CDS (V–) + 1 V V
tON Amplifier enable time (full shutdown) (6) G = 10, VCM = VS / 2, VO = 0.9 × VS / 2,
RL connected to V–		 100 µs
tOFF Amplifier disable time (6) G = 10, VCM = VS / 2, VO = 0.1 × VS / 2,
RL connected to V–		 5 µs
SHDN pin input bias current (per pin) (V+) ≥ SHDN ≥ (V–) + 1 V 10 nA
SHDN pin input bias current (per pin) (V–) ≤ SHDN ≤ (V–) + 0.2 V 175 nA
(1) Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).
(2) Offset drifts are uncorrelated. Input-referred offset drift is calculated using: ΔVOS(RTI) = √[ΔVOSI2 + (ΔVOSO / G)2]
(3) Input common-mode voltage range of the just the input stage of the instrumentation amplifier. The entire INA351 input range depends on the combination input common-mode voltage, differential voltage, gain, reference voltage and power supply voltage. Typical Characteristic curves will be added with more information.
(4) Minimum and Maximum values are specified by characterization.
(5) Total RTI voltage noise is equal to: eN(RTI) = √[eNI2 + (eNO / G)2]
(6) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.