JAJSQA8 june   2023 INA351A

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Gain-Setting
        1. 8.3.1.1 Gain Error and Drift
      2. 8.3.2 Input Common-Mode Voltage Range
      3. 8.3.3 EMI Rejection
      4. 8.3.4 Typical Specifications and Distributions
      5. 8.3.5 Electrical Overstress
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Reference Amplifier
      2. 9.1.2 Input Bias Current Return Path
    2. 9.2 Typical Applications
      1. 9.2.1 Resistive-Bridge Pressure Sensor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Typical Characteristics

at TA = 25°C, VS = (V+) – (V–) = 5.5 V, VIN = (VIN+) – (VIN–) = 0 V, RL = 10 kΩ, CL = 10 pF, VREF = VS / 2, VCM = [(VIN+) + (VIN–)] / 2 = VS / 2, VOUT = VS / 2, VA_IN+ = VS / 2, VA_OUT = VA_IN- and G = 10 (unless otherwise noted)

GUID-20230131-SS0I-SG7S-KZQT-MK4SVSBQQSNR-low.gif
N = 36 μ = 23 μV σ = 0.180 mV
Figure 7-1 Typical Distribution of Input Referred Offset Voltage
GUID-20221130-SS0I-R5QX-DS8L-3RGGBWWZV4RF-low.gif
TA = 25°CN = 72μ = 0.33 pAσ = 0.43 pA
Figure 7-3 Typical Distribution of Input Bias Current
GUID-20221130-SS0I-0PZB-BGBH-74QBLP1RHZF7-low.gif
TA = 85°CN = 72μ = 3.3 pAσ = 0.53 pA
Figure 7-5 Typical Distribution of Input Bias Current
GUID-20221130-SS0I-HWDN-V2MW-W1VFD2ZD23KJ-low.gif
N = 36 μ = -0.30 μV/V σ = 7.10 μV/V
Figure 7-7 Typical Distribution of CMRR
GUID-20221130-SS0I-LJHG-QGNL-G1JSGG0LKN04-low.gif
Figure 7-9 Input Referred Offset Voltage vs Temperature
GUID-20221130-SS0I-MDMT-J4VR-BF7J46QV5NX0-low.gifFigure 7-11 Input Offset Current vs Temperature
GUID-20221130-SS0I-8SLS-G8WL-ZGM7N0S2SN7F-low.gifFigure 7-13 Short Circuit Current vs Temperature
GUID-20230530-SS0I-JZT5-SWRF-V8KV51DLPSKQ-low.gifFigure 7-15 CMRR vs Temperature
GUID-20221130-SS0I-Z13B-JVP1-G5CBM3BGG9ZF-low.gif
V+ = 1.65 V and V– = –1.65 V
Figure 7-17 Input Referred Offset Voltage vs Input Common-Mode Voltage
GUID-20221130-SS0I-S4FL-WSRZ-4XV8MD3RZRGQ-low.gif
V+ = 2.75 V and V– = –2.75 V
Figure 7-19 Input Offset Current vs Input Common-Mode Voltage
GUID-20221130-SS0I-7ZJQ-C0RD-CFW8QLP435TF-low.gif
Figure 7-21 Input Referred Offset Voltage vs Supply Voltage
GUID-20221130-SS0I-T0N3-W1JR-QZVVGRZXMGWP-low.gifFigure 7-23 Output Voltage vs Output Current (Sourcing)
GUID-20230605-SS0I-DBLK-PGBQ-7MTTB2FMRF6K-low.gifFigure 7-25 Closed-Loop Gain vs Frequency
GUID-20230605-SS0I-BZ8G-C3TL-90MNSKHTWDNQ-low.gifFigure 7-27 PSRR+ (Referred to Input) vs Frequency
GUID-20230530-SS0I-MPKD-MCDL-RWFK5RC8ZRG6-low.gifFigure 7-29 Input Referred Voltage Noise Spectral Density
GUID-20221129-SS0I-R5Z9-6HDJ-SH8MKKC89LTM-low.gifFigure 7-31 Closed-Loop Output Impedance vs Frequency
GUID-20230530-SS0I-1LM9-B20J-PSG92FM3FQND-low.gif
VS = 5.5 V BW = 80 kHz VCM = 2.75 V
RL = 10 kΩ VOUT = 0.5 VRMS
Figure 7-33 THD + N Frequency
GUID-20230530-SS0I-RXJF-STJR-TBMXTDJQRCXB-low.gifFigure 7-35 Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency
GUID-20221130-SS0I-WTPH-8MVJ-BDXCXZ4WHJJW-low.gif
V+ = 2.75 V V– = –2.75 V VOUT = 2 VPP
Figure 7-37 Large Signal Step Response
GUID-20221129-SS0I-K21Q-ZQR5-6NVXWQ926K4M-low.gif
V+ = 2.75 V V– = –2.75 V VOUT = 2 VPP
Figure 7-39 Large Signal Settling Time (Rising Edge)
GUID-20221129-SS0I-V47L-GDDT-XWNGPRXQDMX1-low.gif
V+ = 2.75 V V– = –2.75 V VIN = 1 VPP
Figure 7-41 Over-Load Recovery (Rising Edge)
GUID-20221129-SS0I-1RCK-1SLP-NZKD0DNLMP7W-low.gif
V+ = 2.75 V V– = –2.75 V VIN = 0.6 VPP
Figure 7-43 No Phase Reversal
GUID-20221130-SS0I-MVSP-M5Q2-XQQ6HDV4QLXP-low.gif
VS = 5.5 V
Figure 7-45 Input Common-Mode Voltage vs Output Voltage (High CMRR Region)
GUID-20221130-SS0I-7JPT-CRNW-S7SPW3N1B2NF-low.gif
VS = 5.5 V
Figure 7-47 Input Common-Mode Voltage vs Output Voltage
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N = 36 μ = 0.23 μV/°C σ = 0.36 μV/°C
Figure 7-2 Typical Distribution of Input Referred Offset Drift
GUID-20221130-SS0I-6QPH-FG3T-4LVTCLXK61DV-low.gif
TA = 25°CN = 36μ = –0.40 pAσ = 0.47 pA
Figure 7-4 Typical Distribution of Input Offset Current
GUID-20221130-SS0I-Z7ML-PV4C-JBSVH3M7QH1H-low.gif
TA = 85°CN = 36μ = 0.05 pAσ = 0.30 pA
Figure 7-6 Typical Distribution of Input Offset Current
GUID-20221130-SS0I-K7XN-JTGB-NZDWWC1STRSG-low.gif
N = 36 μ = 0.002 % σ = 0.02 %
Figure 7-8 Typical Distribution of Gain Error
GUID-20221130-SS0I-6G93-DNN3-VPSPBPQR63HF-low.gifFigure 7-10 Input Bias Current vs Temperature
GUID-20221130-SS0I-KR73-HNCZ-CT19ZPZTMRBX-low.gifFigure 7-12 Quiescent Current vs Temperature
GUID-20230530-SS0I-26WB-LDWM-4LTTHXPWWMLW-low.gifFigure 7-14 Gain Error vs Temperature
GUID-20221130-SS0I-2QZC-8PBS-VQTHBNSBGQGS-low.gif
V+ = 2.75 V and V– = –2.75 V
Figure 7-16 Input Referred Offset Voltage vs Input Common-Mode Voltage
GUID-20221130-SS0I-X0HH-T0GV-XTRQPGSFTB37-low.gif
V+ = 2.75 V and V– = –2.75 V
Figure 7-18 Input Bias Current vs Input Common-Mode Voltage
GUID-20221130-SS0I-9FPR-JBWW-BKMCH4BNRWCN-low.gif
V+ = 2.75 V and V– = –2.75 V
Figure 7-20 Quiescent Current vs Input Common-Mode Voltage
GUID-20221130-SS0I-J7FW-5XFB-7BXSDGKRTSJ7-low.gif
 
Figure 7-22 Quiescent Current vs Supply Voltage
GUID-20221130-SS0I-57W8-T3TT-HV0DDB3NQJJM-low.gifFigure 7-24 Output Voltage vs Output Current (Sinking)
GUID-20230530-SS0I-RVF1-TMSJ-WN7MRMB7CMWR-low.gifFigure 7-26 CMRR (Referred to Input) vs Frequency
GUID-20230530-SS0I-VPKW-TSZD-9N7GQTHPNJPJ-low.gifFigure 7-28 PSRR– (Referred to Input) Vs Frequency
GUID-20221129-SS0I-32WB-VBSL-HJKLNBWZMZP1-low.gifFigure 7-30 0.1 Hz to 10 Hz Voltage Noise in Time Domain
GUID-20221129-SS0I-GRVK-2MWL-CTXVZJNSMWFW-low.gifFigure 7-32 Maximum Output Voltage vs Frequency
GUID-20230530-SS0I-TTQZ-STMV-TDQ1S9SS4HCB-low.gif
VS = 5.5 V BW = 80 kHz VCM = 2.75 V
RL = 100 kΩ VOUT = 1 VRMS
Figure 7-34 THD + N Frequency
GUID-20221129-SS0I-7DLW-TBML-F90Z1H45RPXX-low.gif
VS = 5.5 V VOUT = 100 mVPP
Figure 7-36 Small-Signal Overshoot vs Capacitive Load
GUID-20221129-SS0I-NLFG-XCHQ-QHPW43QTSN6Z-low.gif
V+ = 2.75 V V– = –2.75 V VOUT = 2 VPP
Figure 7-38 Large Signal Settling Time (Falling Edge)
GUID-20221129-SS0I-BLH6-SW9C-CHFPZBW9GW70-low.gif
V+ = 2.75 V V– = –2.75 V VOUT = 0.1 VPP
Figure 7-40 Small-Signal Step Response
GUID-20221129-SS0I-1VVF-CL9D-PVJNRQWJWD00-low.gif
V+ = 2.75 V V– = –2.75 V VIN = 1 VPP
Figure 7-42 Over-Load Recovery (Falling Edge)
GUID-20221130-SS0I-SCMW-NT7Q-GB4XDDN6GNG5-low.gif
VS = 3.3 V
Figure 7-44 Input Common-Mode Voltage vs Output Voltage (High CMRR Region)
GUID-20221130-SS0I-HJFJ-X09X-HNWB5C5NWNBF-low.gif
VS = 3.3 V
Figure 7-46 Input Common-Mode Voltage vs Output Voltage