JAJSLD8B July 2021 – November 2021 INA823
PRODUCTION DATA
The gain of the IA is calculated so that the circuit operates at unity gain, where VOUT = VDIFF.
The single-ended input impedance, Rin(SE), of the circuit is the sum of the scaling resistors (Rf + Ri). To minimize the error that is caused by the tolerance of the scaling resistors, keep Rin > 1 MΩ.
Ideally, choose the resistors so that Rf / Ri = Rf' / Ri'. In the real world, designers have to trade off between the mismatch of ratios that degrades the common-mode rejection ratio (CMRR) and the acceptable cost for the design.
The following text describe how to estimate the CMRR performance of the external resistor scaling approach. In the calculation of CMRR, the following factors are considered:
Equation 9 calculates the common-mode rejection ratio with given factors:
The scaling ratio G1 is calculated by:
where
Figure 9-6 shows a comparison between the CMRR performance at worst-case (α neglected) and considering normal distribution for different gain settings of G1.
For more details about the calculation of CMRR, see the Difference amplifier (subtractor) circuit analog engineer's circuit.