JAJSOA9A
March 2022 – October 2022
INA851
PRODUCTION DATA
1
特長
2
アプリケーション
3
説明
4
Revision History
5
Related Products
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Adjustable Gain Setting
8.3.1.1
Gain Drift
8.3.2
Offset Voltage
8.3.3
Input Common-Mode Range
8.3.4
Input Protection
8.3.5
Output Clamping
8.3.6
Low Noise
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.1.1
Output Common-Mode Pin
9.1.2
Output-Stage Gain Selection and Noise-Gain Shaping
9.1.3
Input Bias Current Return Path
9.1.4
Thermal Effects due to Power Dissipation
9.2
Typical Applications
9.2.1
Three-Pin Programmable Logic Controller (PLC)
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
アプリケーション曲線
9.2.2
20-Bit, 1-MSPS ADS8900B Driver Circuit With FDA Noise Filter
9.2.2.1
Design Requirements
9.2.2.2
Application Curves
9.2.3
24-Bit, 200 kSPS, Delta-Sigma ADS127L11 ADC Driver Circuit With FDA Noise Filter
9.2.3.1
Design Requirements
9.2.3.2
Application Curves
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Device Support
10.1.1
Development Support
10.1.1.1
PSpice® for TI
10.1.1.2
TINA-TI™シミュレーション・ソフトウェア (無償ダウンロード)
10.2
Documentation Support
10.2.1
Related Documentation
10.3
Receiving Notification of Documentation Updates
10.4
サポート・リソース
10.5
Trademarks
10.6
Electrostatic Discharge Caution
10.7
Glossary
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RGT|16
MPQF119H
サーマルパッド・メカニカル・データ
RGT|16
QFND098S
発注情報
jajsoa9a_oa
jajsoa9a_pm
8
Detailed Description