JAJSDX8E June   2017  – August 2018 ISO1211 , ISO1212

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション図
      2.      従来のソリューションと比較した、ISO121xデバイスによる基板の温度の低下
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics—DC Specification
    10. 7.10 Switching Characteristics—AC Specification
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Sinking Inputs
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Setting Current Limit and Voltage Thresholds
          2. 10.2.1.2.2 Thermal Considerations
          3. 10.2.1.2.3 Designing for 48-V Systems
          4. 10.2.1.2.4 Designing for Input Voltages Greater Than 60 V
          5. 10.2.1.2.5 Surge, ESD, and EFT Tests
          6. 10.2.1.2.6 Multiplexing the Interface to the Host Controller
          7. 10.2.1.2.7 Status LEDs
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Sourcing Inputs
      3. 10.2.3 Sourcing and Sinking Inputs (Bidirectional Inputs)
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
サーマルパッド・メカニカル・データ
発注情報

7.9 Electrical Characteristics—DC Specification

(Over recommended operating conditions unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC1 VOLTAGE SUPPLY
VIT+ (UVLO1) Positive-going UVLO threshold voltage (VCC1) 2.25 V
VIT– (UVLO1) Negative-going UVLO threshold (VCC1) 1.7 V
VHYS (UVLO1) UVLO threshold hysteresis (VCC1) 0.2 V
ICC1 VCC1 supply quiescent current ISO1211 EN = VCC1 0.6 1 mA
ISO1212 1.2 1.9
LOGIC I/O
VIT+ (EN) Positive-going input logic threshold voltage for EN pin 0.7 × VCC1 V
VIT– (EN) Negative-going input logic threshold voltage for EN pin 0.3 × VCC1 V
VHYS(EN) Input hysteresis voltage for EN pin 0.1 × VCC1 V
IIH Low-level input leakage at EN pin EN = GND1 –10 μA
VOH High-level output voltage on OUTx VCC1 = 4.5 V; IOH = –4 mA
VCC1 = 3 V; IOH = –3 mA
VCC1= 2.25 V; IOH = –2 mA, see Figure 10 		VCC1 – 0.4 V
VOL Low-level output voltage on OUTx VCC1 = 4.5 V; IOH = 4 mA
VCC1 = 3 V; IOH = 3 mA
VCC1= 2.25 V ; IOH = 2 mA, see Figure 10 		0.4 V
CURRENT LIMIT
I(INx+SENSEx),TYP Typical sum of current drawn from IN and SENSE pins across temperature RTHR = 0 Ω, RSENSE = 562 Ω, VSENSE = 24 V,
–40°C < TA < 125°C, see Figure 11 		2.2 2.47 mA
I(INx+SENSEx) Sum of current drawn from IN and SENSE pins RTHR = 0 Ω, RSENSE = 562 Ω ± 1%;
–60 V < VSENSE < 0 V, see Figure 11 		–0.1 µA
RTHR = 0 Ω, RSENSE = 562 Ω ± 1%;
5 V < VSENSE < VIL, see Figure 11 		1.9 2.5 mA
RTHR = 0 Ω, RSENSE = 562 Ω ± 1%;
VIL < VSENSE < 30 V, see Figure 11 		2.05 2.75
RTHR = 0 Ω, RSENSE = 562 Ω ± 1%;
30 V < VSENSE < 36 V, see Figure 11 		2.1 2.83
RTHR = 0 Ω, RSENSE = 562 Ω ± 1%;
36 V < VSENSE < 60 V(1), see Figure 11 		2.1 3.1
RTHR = 0 Ω, RSENSE = 200 Ω ± 1%;
–60 V < VSENSE < 0 V, see Figure 11 		–0.1 µA
RTHR = 0 Ω, RSENSE = 200 Ω ± 1%;
5 V < VSENSE < VIL, see Figure 11 		5.3 6.8 mA
RTHR = 0 Ω, RSENSE = 200 Ω ± 1%;
VIL < VSENSE < 36 V(1), see Figure 11 		5.5 7
RTHR = 0 Ω, RSENSE = 200 Ω ± 1%;
36 V < VSENSE < 60 V(1), see Figure 11 		5.5 7.3
VOLTAGE TRANSITION THRESHOLD ON FIELD SIDE
VIL Low level threshold voltage at module input (including RTHR) for output high RSENSE = 562 Ω, RTHR = 0 Ω, see Figure 11 6.5 7 V
RSENSE = 562 Ω, RTHR = 1 kΩ, see Figure 11 8.7 9.2
RSENSE = 562 Ω, RTHR = 4 kΩ, see Figure 11 15.2 15.8
VIH High level threshold voltage at module input (including RTHR) for output low RSENSE = 562 Ω, RTHR = 0 Ω, see Figure 11 8.2 8.55 V
RSENSE = 562 Ω, RTHR = 1 kΩ, see Figure 11 10.4 10.95
RSENSE = 562 Ω, RTHR = 4 kΩ, see Figure 11 17 18.25
VHYS Threshold voltage hysteresis at module input RSENSE = 562 Ω, RTHR = 0 Ω, see Figure 11 1 1.2 V
RSENSE = 562 Ω, RTHR = 1 kΩ, see Figure 11 1 1.2
RSENSE = 562 Ω, RTHR = 4 kΩ, see Figure 11 1 1.2
(1) See the Thermal Considerations section.