JAJSCQ8D November   2016  – December 2022 ISO1540-Q1 , ISO1541-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Supply Current Characteristics
    11. 6.11 Timing Requirements
    12. 6.12 Switching Characteristics
    13. 6.13 Insulation Characteristics Curves
    14. 6.14 Typical Characteristics
      1.      Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
    4. 7.4 Isolator Functional Principle
      1. 7.4.1 Receive Direction (Left Diagram of )
      2. 7.4.2 Transmit Direction (Right Diagram of )
    5. 7.5 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 I2C Bus Overview
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Material
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.9 Electrical Characteristics

over recommended operating conditions, unless otherwise noted
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SIDE 1 (ONLY)
VILT1Voltage input threshold low, SDA1 and SCL1480550660mV
VIHT1Voltage input threshold high, SDA1 and SCL1520610700mV
VHYST1Voltage input hysteresisVIHT1 –VILT14060mV
VOL1Low-level output voltage, SDA1 and SCL1(1)0.5 mA ≤ (ISDA1 and ISCL1) ≤ 3.5 mA570800mV
ΔVOIT1Low-level output voltage to high-level input voltage threshold difference, SDA1 and SCL1(1)(2)0.5 mA ≤ (ISDA1 and ISCL1) ≤ 3.5 mA50mV
SIDE 2 (ONLY)
VILT2Voltage input threshold low, SDA2 and SCL20.3 × VCC20.4 × VCC2V
VIHT2Voltage input threshold high, SDA2 and SCL20.4 × VCC20.5 × VCC2V
VHYST2Voltage input hysteresisVIHT2 – VILT20.05 × VCC2V
VOL2Low-level output voltage, SDA2 and SCL20.5 mA ≤ (ISDA2 and ISCL2) ≤ 35 mA0.4V
BOTH SIDES
|II|Input leakage currents, SDA1, SCL1, SDA2, and SCL2VSDA1, VSCL1 = VCC1;
VSDA2, VSCL2 = VCC2		0.0110µA
CIInput capacitance to local ground, SDA1, SCL1, SDA2, and SCL2VI = 0.4 × sin(2E6πt) + 2.5 V7pF
CMTICommon-mode transient immunitySee Figure 7-32550kV/µs
VCCUVVCC undervoltage lockout threshold(3)1.72.52.9V
(1) This parameter does not apply to the ISO1541-Q1 SCL1 line as it is unidirectional.
(2) ∆VOIT1 = VOL1 – VIHT1. This represents the minimum difference between a Low-Level Output Voltage and a High-Level Input Voltage Threshold to prevent a permanent latch condition that would otherwise exist with bidirectional communication.
(3) Any VCC voltages, on either side, less than the minimum will ensure device lockout. Both VCC voltages greater than the maximum will prevent device lockout.