JAJSCQ8D November   2016  – December 2022 ISO1540-Q1 , ISO1541-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Supply Current Characteristics
    11. 6.11 Timing Requirements
    12. 6.12 Switching Characteristics
    13. 6.13 Insulation Characteristics Curves
    14. 6.14 Typical Characteristics
      1.      Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
    4. 7.4 Isolator Functional Principle
      1. 7.4.1 Receive Direction (Left Diagram of )
      2. 7.4.2 Transmit Direction (Right Diagram of )
    5. 7.5 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 I2C Bus Overview
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Material
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Insulation Specifications

PARAMETERTEST CONDITIONSVALUEUNIT
GENERAL
CLRExternal clearance(1)Shortest terminal-to-terminal distance through air>4mm
CPGExternal creepage(1)Shortest terminal-to-terminal distance across the package surface>4mm
DTIDistance through the insulationMinimum internal gap (internal clearance)0.014mm
CTIComparative tracking indexDIN EN 60112 (VDE 0303-11); IEC 60112>400V
Material group II
Overvoltage categoryRated mains voltage ≤ 150 VRMSI–IV
Rated mains voltage ≤ 300 VRMSI–III
DIN EN IEC 60747-17 (VDE 0884-17)(2)
VIORMMaximum repetitive peak isolation voltageAC voltage (bipolar)566VPK
VIOTMMaximum transient isolation voltageVTEST = VIOTM
t = 60 s (qualification)
t = 1 s (100% production)		4242VPK
qpdApparent charge(3)Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 680 VPK, tm = 10 s<5pC
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM = 906 VPK, tm = 10 s<5
Method b1: At routine test (100% production) and preconditioning (type test) Vini = VIOTM, tini = 1 s; Vpd(m) = 1.875 × VIORM = 1062 VPK, tm = 1 s<5
CIOBarrier capacitance, input to output(4)VIO = 0.4 sin (2πft), f = 1 MHz~1pF
RIOIsolation resistance, input to output(4)VIO = 500 V, TA = 25°C>1012Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C>1011
VIO = 500 V at TS = 150°C>109
Pollution degree2
Climatic category40/125/21
UL 1577
VISOWithstand isolation voltageVTEST = VISO = 2500 VRMS, t = 60 s (qualification); VTEST = 1.2 × VISO = 3000 VRMS, t = 1 s (100% production)2500VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Apparent charge is electrical discharge caused by a partial discharge (pd).
(4) All pins on each side of the barrier tied together creating a two-terminal device