The I²C bus consists of a two-wire communication bus that supports bidirectional data transfer between a master device and several slave devices. The master, or processor, controls the bus, specifically the serial clock (SCL) line. Data is transferred between the master and slave through a serial data (SDA) line. This data can be transferred in four speeds: standard mode (0 to 100 kbps), fast mode (0 to 400 kbps), fast-mode plus (0 to 1 Mbps), and high-speed mode (0 to 3.4 Mbps).

The I²C bus operates in bidirectional, half-duplex mode, using open collector outputs to allow for multiple devices to share the bus. When a specific device is ready to communicate on the bus, it can take control pulling the lines low accordingly in order to transmit data. A standard digital isolator or optocoupler is designed to transfer data in a single direction. In order to support an I²C bus, external circuitry is required to separate the bidirectional bus into two unidirectional signal paths. The ISO164x-Q1 devices internally handle the separation and partitioning of the transmit and receive signals, integrating the external circuitry needed and provide the open-collector signals. They provide high electromagnetic immunity and low emissions at low power consumption. Each isolation channel has a logic input and output buffer separated by TI's double capacitive silicon dioxide (SiO2) insulation barrier. When used in conjunction with isolated power supplies, these devices block high voltages, isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging sensitive circuitry.