JAJSQF6D june   2015  – may 2023 ISO5451

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 説明
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Pin Configuration and Function
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Characteristics
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Supply and Active Miller Clamp
      2. 9.3.2 Active Output Pull-down
      3. 9.3.3 Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication Output
      4. 9.3.4 Fault ( FLT) and Reset ( RST)
      5. 9.3.5 Short Circuit Clamp
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Recommended ISO5451 Application Circuit
        2. 10.2.2.2  FLT and RDY Pin Circuitry
        3. 10.2.2.3  Driving the Control Inputs
        4. 10.2.2.4  Local Shutdown and Reset
        5. 10.2.2.5  Global-Shutdown and Reset
        6. 10.2.2.6  Auto-Reset
        7. 10.2.2.7  DESAT Pin Protection
        8. 10.2.2.8  DESAT Diode and DESAT Threshold
        9. 10.2.2.9  Determining the Maximum Available, Dynamic Output Power, POD-max
        10. 10.2.2.10 Example
        11. 10.2.2.11 Higher Output Current Using an External Current Buffer
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 PCB Material
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 サード・パーティ製品に関する免責事項
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DW|16
サーマルパッド・メカニカル・データ
発注情報

7.6 Insulation Characteristics

PARAMETERTEST CONDITIONSSPECIFICATIONUNIT
CLRExternal clearance(1)Shortest terminal-to-terminal distance through air>8mm
CPGExternal creepage(1)Shortest terminal-to-terminal distance across the package surface>8mm
DTIDistance through the insulationMinimum internal gap (internal clearance)>21μm
CTITracking resistance (comparative tracking index)DIN EN 60112 (VDE 0303-11); IEC 60112;
UL 746A		>600V
Material GroupAccording to IEC 60664-1I
Overvoltage category (according to IEC 60664-1)Rated Mains Voltage ≤ 300 VRMSI-IV
Rated Mains Voltage ≤ 600 VRMSI-III
Rated Mains Voltage ≤ 1000 VRMSI-II
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(2)
VIORMMaximum repetitive peak isolation voltageAC voltage (bipolar)1420VPK
VIOWMMaximum isolation working voltageAC voltage. Time dependent dielectric breakdown (TDDB) Test, see Figure 7-11000VRMS
DC voltage1420VDC
VIOTMMaximum Transient isolation voltageVTEST = VIOTM, t = 60 sec (qualification), t = 1 sec (100% production)8000VPK
VIOSMMaximum surge isolation voltage(3)Test method per IEC 60065, 1.2/50 μs waveform,
VTEST = 1.6 × VIOSM = 10000 VPK (qualification)(3)		6250
qpdApparent charge(4)Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 1704 VPK ,
tm = 10 s		≤5pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 2272 VPK ,
tm = 10 s		≤5
Method b1: At routine test (100% production) and preconditioning (type test)
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.875 × VIORM = 2663 VPK ,
tm = 10 s		≤5
RIOIsolation resistance, input to output(5)VIO = 500 V, TA = 25°C> 1012Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C> 1011Ω
VIO = 500 V at TS = 150°C> 109Ω
CIOBarrier capacitance, input to output(5)VIO = 0.4 × sin (2πft), f = 1 MHz~1pF
Pollution degree2
Climatic category40/125/21
UL 1577
VISOWithstanding Isolation voltageVTEST = VISO, t = 60 sec (qualification),
VTEST = 1.2 × VISO = 6840 VRMS,
t = 1 sec (100% production)		5700VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device