JAJSQG0C june   2015  – may 2023 ISO5851

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Pin Configuration and Function
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Characteristics
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Supply and Active Miller Clamp
      2. 9.3.2 Active Output Pulldown
      3. 9.3.3 Undervoltage Lockout (UVLO) With Ready (RDY) Pin Indication Output
      4. 9.3.4 Fault ( FLT) and Reset ( RST)
      5. 9.3.5 Short Circuit Clamp
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Recommended ISO5851 Application Circuit
        2. 10.2.2.2  FLT and RDY Pin Circuitry
        3. 10.2.2.3  Driving the Control Inputs
        4. 10.2.2.4  Local Shutdown and Reset
        5. 10.2.2.5  Global-Shutdown and Reset
        6. 10.2.2.6  Auto-Reset
        7. 10.2.2.7  DESAT Pin Protection
        8. 10.2.2.8  DESAT Diode and DESAT Threshold
        9. 10.2.2.9  Determining the Maximum Available, Dynamic Output Power, POD-max
        10. 10.2.2.10 Example
        11. 10.2.2.11 Higher Output Current Using an External Current Buffer
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 PCB Material
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 サード・パーティ製品に関する免責事項
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DW|16
サーマルパッド・メカニカル・データ
発注情報

7.9 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE SUPPLY
VIT+(UVLO1) Positive-going UVLO1 threshold voltage input side (VCC1 – GND1) 2.25 V
VIT-(UVLO1) Negative-going UVLO1 threshold voltage input side (VCC1 – GND1) 1.7 V
VHYS(UVLO1) UVLO1 Hysteresis voltage (VIT+ – VIT–) input side 0.24 V
VIT+(UVLO2) Positive-going UVLO2 threshold voltage output side (VCC2 – GND2) 12 13 V
VIT-(UVLO2) Negative-going UVLO2 threshold voltage output side (VCC2 – GND2) 9.5 11 V
VHYS(UVLO2) UVLO2 Hysteresis voltage (VIT+ – VIT–) output side 1 V
IQ1 Input supply quiescent current 2.8 4.5 mA
IQ2 Output supply quiescent current 3.6 6 mA
LOGIC I/O
VIT+(IN, RST) Positive-going input threshold voltage (IN+, IN–, RST) 0.7 × VCC1 V
VIT-(IN, RST) Negative-going input threshold voltage (IN+, IN–, RST) 0.3 × VCC1 V
VHYS(IN, RST) Input hysteresis voltage (IN+, IN–, RST) 0.15 × VCC1 V
IIH High-level input leakage at (IN+) IN+ = VCC1 100 µA
IIL Low-level input leakage at (IN–, RST) IN– = GND1, RST = GND1 –100 µA
IPU Pull-up current of FLT, RDY V(RDY) = GND1, V(FLT) = GND1 100 µA
VOL Low-level output voltage at FLT, RDY I(FLT) = 5 mA 0.2 V
GATE DRIVER STAGE
V(OUTPD) Active output pulldown voltage IOUT = 200 mA, VCC2 = open 2 V
V(OUTH) High-level output voltage IOUT = –20 mA VCC2 – 0.5 VCC2 – 0.24 V
V(OUTL) Low-level output voltage IOUT = 20 mA VEE2 + 13 VEE2 + 50 mV
I(OUTH) High-level output peak current IN+ = high, IN– = low,
VOUT = VCC2 - 15 V		 1.5 2.5 A
I(OUTL) Low-level output peak current IN+ = low, IN– = high,
VOUT = VEE2 + 15 V		 3.4 5 A
ACTIVE MILLER CLAMP
V(CLP) Low-level clamp voltage I(CLP) = 20 mA VEE2 + 0.015 VEE2 + 0.08 V
I(CLP) Low-level clamp current V(CLAMP) = VEE2 + 2.5 V 1.6 2.5 A
V(CLTH) Clamp threshold voltage 1.6 2.1 2.5 V
SHORT CIRCUIT CLAMPING
V(CLP_OUT) Clamping voltage
(VOUT - VCC2)		 IN+ = high, IN– = low, tCLP = 10 µs, I(OUTH) = 500 mA 0.8 1.3 V
V(CLP_CLAMP) Clamping voltage
(VCLP - VCC2)		 IN+ = high, IN– = low, tCLP = 10 µs, I(CLP) = 500 mA 1.3 V
V(CLP_CLAMP) Clamping voltage at CLAMP IN+ = High, IN– = Low, I(CLP) = 20 mA 0.7 1.1 V
DESAT PROTECTION
I(CHG) Blanking capacitor charge current V(DESAT) - GND2 = 2 V 0.42 0.5 0.58 mA
I(DCHG) Blanking capacitor discharge current V(DESAT) - GND2 = 6 V 9 14 mA
V(DSTH) DESAT threshold voltage with respect to GND2 8.3 9 9.5 V
V(DSL) DESAT voltage with respect to GND2, when OUT is driven low 0.4 1 V