JAJSCW6
December 2016
ISO5852S-EP
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
4
改訂履歴
5
概要(続き)
6
Pin Configuration and Function
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Power Ratings
7.6
Insulation Specifications
7.7
Safety Limiting Values
7.8
Safety-Related Certifications
7.9
Electrical Characteristics
7.10
Switching Characteristics
7.11
Insulation Characteristics Curves
7.12
Typical Characteristics
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Supply and Active Miller clamp
9.3.2
Active Output Pulldown
9.3.3
Undervoltage Lockout (UVLO) With Ready (RDY) Pin Indication Output
9.3.4
Soft Turnoff, Fault (FLT) and Reset (RST)
9.3.5
Short Circuit Clamp
9.4
Device Functional Modes
10
Application and Implementation
10.1
Application Information
10.2
Typical Applications
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Recommended ISO5852S-EP Application Circuit
10.2.2.2
FLT and RDY Pin Circuitry
10.2.2.3
Driving the Control Inputs
10.2.2.4
Local Shutdown and Reset
10.2.2.5
Global-Shutdown and Reset
10.2.2.6
Auto-Reset
10.2.2.7
DESAT Pin Protection
10.2.2.8
DESAT Diode and DESAT Threshold
10.2.2.9
Determining the Maximum Available, Dynamic Output Power, POD-max
10.2.2.10
Example
10.2.2.11
Higher Output Current Using an External Current Buffer
10.2.3
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
PCB Material
12.3
Layout Example
13
デバイスおよびドキュメントのサポート
13.1
ドキュメントのサポート
13.1.1
関連資料
13.2
ドキュメントの更新通知を受け取る方法
13.3
コミュニティ・リソース
13.4
商標
13.5
静電気放電に関する注意事項
13.6
用語集
14
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DW|16
MSOI003I
サーマルパッド・メカニカル・データ
DW|16
QFND505A
発注情報
jajscw6_oa
8
Parameter Measurement Information
Figure 44.
OUTH and OUTL Propagation Delay, Non-Inverting Configuration
Figure 45.
OUTH and OUTL Propagation Delay, Inverting Configuration
Figure 46.
DESAT, OUTH/L,
FLT
,
RST
Delay
Figure 47.
Common-Mode Transient Immunity Test Circuit