JAJSKK4A December   2019  – June 2021 ISO6731-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics—5-V Supply
    10. 6.10 Supply Current Characteristics—5-V Supply
    11. 6.11 Electrical Characteristics—3.3-V Supply
    12. 6.12 Supply Current Characteristics—3.3-V Supply
    13. 6.13 Electrical Characteristics—2.5-V Supply 
    14. 6.14 Supply Current Characteristics—2.5-V Supply
    15. 6.15 Electrical Characteristics—1.8-V Supply
    16. 6.16 Supply Current Characteristics—1.8-V Supply
    17. 6.17 Switching Characteristics—5-V Supply
    18. 6.18 Switching Characteristics—3.3-V Supply
    19. 6.19 Switching Characteristics—2.5-V Supply
    20. 6.20 Switching Characteristics—1.8-V Supply
    21. 6.21 Insulation Characteristics Curves
    22. 6.22 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Electromagnetic Compatibility (EMC) Considerations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
        1. 9.2.3.1 Insulation Lifetime
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
    2. 13.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-20201228-CA0I-ZSXD-FQP6-S8QQ9XKTHGPW-low.gif Figure 5-1 ISO6731-Q1 DW Package16-Pin SOIC-WBTop View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME ISO6731-Q1
EN1 7 I Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in high-impedance state when EN1 is low.
EN2 10 I Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in high-impedance state when EN2 is low.
GND1 2, 8 — Ground connection for VCC1
GND2 9,15 — Ground connection for VCC2
INA 3 I Input, channel A
INB 4 I Input, channel B
INC 12 I Input, channel C
NC 6,11 Not connected
OUTA 14 O Output, channel A
OUTB 13 O Output, channel B
OUTC 5 O Output, channel C
VCC1 1 — Power supply, side 1
VCC2 16 — Power supply, side 2