JAJSVM9B
September 2010 – November 2024
ISO7240CF-Q1
,
ISO7241C-Q1
,
ISO7242C-Q1
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configurations and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Characteristics
5.5
Power Ratings
5.6
Safety-Related Certifications
5.7
Safety Limiting Values
5.8
Insulation Specifications
5.9
Electrical Characteristics: VCC1 and VCC2 at 5-V Operation
5.10
Electrical Characteristics: VCC1 and VCC2 at 3.3 V Operation
5.11
Electrical Characteristics: VCC1 at 3.3-V, VCC2 at 5-V Operation
5.12
Electrical Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
5.13
Switching Characteristics: VCC1 and VCC2 at 3.3-V Operation
5.14
Switching Characterstics: VCC1 and VCC2 at 5-V Operation
5.15
Switching Characteristics: VCC1 at 3.3-V and VCC2 at 5-V Operation
5.16
Switching Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
5.17
Insulation Characteristics Curves
5.18
Typical Characteristic
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.4
Device Functional Modes
7.4.1
Device I/O Schematics
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Isolated Data Acquisition System for Process Control
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.2
Isolated SPI for an Analog Input Module with 16 Inputs
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.3
Isolated RS-232 Interface
8.2.3.1
Design Requirements
8.2.3.2
Detailed Design Procedure
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.1.1
PCB Material
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Related Links
9.3
ドキュメントの更新通知を受け取る方法
9.4
サポート・リソース
9.5
Trademarks
9.6
静電気放電に関する注意事項
9.7
用語集
10
Revision History
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DW|16
MSOI003I
サーマルパッド・メカニカル・データ
DW|16
QFND505A
発注情報
jajsvm9b_oa
jajsvm9b_pm
7.2
Functional Block Diagram
Figure 7-1
Conceptual Block Diagram of a Digital Isolator