SLLSEK5 Data sheet

SLLSEK5B July 2015 – May 2017 ISO7340-Q1 , ISO7341-Q1 , ISO7342-Q1

PRODUCTION DATA.

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DW|16

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7 Specifications

7.1 Absolute Maximum Ratings

See ⁽¹⁾

			MIN	MAX	UNIT
V_CC	Supply voltage⁽²⁾	V_CC1, V_CC2	–0.5	6	V
	Voltage	INx, OUTx, ENx	–0.5	V_CC + 0.5⁽³⁾	V
I_O	Output current			±15	mA
T_J	Maximum junction temperature			150	°C
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.

(3) Maximum voltage must not exceed 6 V.

7.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾		±4000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011		±1500	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
V_CC1, V_CC2	Supply voltage	3		5.5	V
I_OH	High-level output current	–4			mA
I_OL	Low-level output current			4	mA
V_IH	High-level input voltage	2		5.5	V
V_IL	Low-level input voltage	0		0.8	V
t_ui	Input pulse duration	40			ns
1 / t_ui	Signaling rate	0		25	Mbps
T_J	Junction temperature⁽¹⁾			136	°C
T_A	Ambient temperature	–40	25	125	°C

(1) To maintain the recommended operating conditions for T_J, see the Thermal Information table.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		ISO734x-Q1	UNIT
		DW (SOIC)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	78.4	°C/W
R_θJC(top)	Junction-to-case(top) thermal resistance	41	°C/W
R_θJB	Junction-to-board thermal resistance	43	°C/W
ψ_JT	Junction-to-top characterization parameter	15.6	°C/W
ψ_JB	Junction-to-board characterization parameter	42.5	°C/W
R_θJC(bottom)	Junction-to-case(bottom) thermal resistance	n/a	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Power Ratings

V_CC1 = V_CC2 = 5.5 V, T_J = 150°C, C_L = 15 pF, Input a 12.5-MHz 50% duty cycle square wave

PARAMETER		MAX	UNIT
P_D	Maximum power dissipation by both sides of ISO7340-Q1	92	mW
P_D1	Maximum power dissipation by side-1 of ISO7340-Q1	24
P_D2	Maximum power dissipation by side-2 of ISO7340-Q1	68
P_D	Maximum power dissipation by both sides of ISO7341-Q1	102	mW
P_D1	Maximum power dissipation by side-1 of ISO7341-Q1	42
P_D2	Maximum power dissipation by side-2 of ISO7341-Q1	60
P_D	Maximum power dissipation by both sides of ISO7342-Q1	111	mW
P_D1	Maximum power dissipation by side-1 of ISO7342-Q1	55.5
P_D2	Maximum power dissipation by side-2 of ISO7342-Q1	55.5

7.6 Insulation Specifications

PARAMETER		TEST CONDITIONS	VALUE	UNIT
GENERAL
CLR	External clearance⁽¹⁾	Shortest terminal-to-terminal distance through air	>8	mm
CPG	External creepage⁽¹⁾	Shortest terminal-to-terminal distance across the package surface	>8	mm
DTI	Distance through the insulation	Minimum internal gap (internal clearance)	>13	µm
CTI	Comparative tracking index	DIN EN 60112 (VDE 0303-11); IEC 60112	>400	V
	Material group		II
	Overvoltage Category	Rated mains voltage ≤ 300 V_RMS	I–IV
		Rated mains voltage ≤ 600 V_RMS	I–III
		Rated mains voltage ≤ 1000 V_RMS	I-II
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12⁽²⁾
V_IORM	Maximum repetitive peak isolation voltage	AC voltage (bipolar)	1414	V_PK
V_IOTM	Maximum transient isolation voltage	V_TEST = V_IOTM; t = 60 s (qualification); t = 1 s (100% production)	4242	V_PK
V_IOSM	Maximum surge isolation voltage⁽³⁾	Test method per IEC 60065, 1.2/50 µs waveform, V_TEST = 1.3 × V_IOSM = 7800 V_PK (qualification)	6000	V_PK
q_pd	Apparent charge⁽⁴⁾	Method a: After I/O safety test subgroup 2/3, V_ini = V_IOTM, t_ini = 60 s; V_pd(m) = 1.2 × V_IORM = 1697 V_PK, t_m = 10 s	≤5	pC
		Method a: After environmental tests subgroup 1, V_ini = V_IOTM, t_ini = 60 s; V_pd(m) = 1.6 × V_IORM = 2262 V_PK, t_m = 10 s	≤5
		Method b1: At routine test (100% production) and preconditioning (type test) V_ini = V_IOTM, t_ini = 1 s; V_pd(m) = 1.875 × V_IORM = 2651 V_PK, t_m = 1 s (100% production)	≤5
C_IO	Barrier capacitance, input to output⁽⁵⁾	V_IO = 0.4 sin (2πft), f = 1 MHz	2.4	pF
R_IO	Isolation resistance, input to output⁽⁵⁾	V_IO = 500 V, T_A = 25°C	>10¹²	Ω
		V_IO = 500 V, 100°C ≤ T_A ≤ x°C	>10¹¹
		V_IO = 500 V at T_S = 150°C	>10⁹
	Pollution degree		2
	Climatic category		40/125/21
UL 1577
V_ISO	Withstand isolation voltage	V_TEST = V_ISO = 3000 V_RMS, t = 60 s (qualification); V_TEST = 1.2 × V_ISO = 3600 V_RMS, t = 1 s (100% production)	3000	V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-terminal device

7.7 Safety-Related Certifications

VDE	CSA	UL	CQC
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 61010-1 (VDE 0411-1):2011-07	Approved under CSA Component Acceptance Notice 5A, IEC 60950-1, and IEC 61010-1	Recognized component under UL 1577	Certified according to GB4943.1-2011
Basic Insulation; Maximum Transient Overvoltage, 4242 V_PK; Maximum Surge Isolation Voltage, 6000 V_PK; Maximum Repetitive Peak Isolation Voltage, 1414 V_PK	800 V_RMS Basic Insulation and 400 V_RMS Reinforced Insulation working voltage per CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed.+A1+A2; 300 V_RMS Basic Insulation working voltage per CSA 61010-1-12 and IEC 61010-1 3rd Ed.	Single protection, 3000 V_RMS	Reinforced Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 V_RMS maximum working voltage
Certificate number: 40016131	Master contract number: 220991	File number: E181974	Certificate number: CQC15001121716

7.8 Safety Limiting Values

Safety limiting⁽¹⁾ intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.

PARAMETER		TEST CONDITIONS	MAX	UNIT
I_S	Safety input, output, or supply current	R_θJA = 78.4 °C/W, V_I = 5.5 V, T_J = 150°C, T_A = 25°C, see Figure 1	290	mA
I_S	Safety input, output, or supply current	R_θJA = 78.4 °C/W, V_I = 3.6 V, T_J = 150°C, T_A = 25°C, see Figure 1	443	mA
T_S	Safety temperature		150

(1) The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

7.9 Electrical Characteristics—5-V Supply

V_CC1 and V_CC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –4 mA; see Figure 14	V_CCO⁽¹⁾ – 0.5	4.7		V
V_OH	High-level output voltage	I_OH= –20 μA; see Figure 14	V_CCO⁽¹⁾ – 0.1	5		V
V_OL	Low-level output voltage	I_OL = 4 mA; see Figure 14		0.2	0.4	V
V_OL	Low-level output voltage	I_OL = 20 μA; see Figure 14		0	0.1	V
V_I(HYS)	Input threshold voltage hysteresis			480		mV
I_IH	High-level input current	V_IH = V_CC at INx or ENx			10	μA
I_IL	Low-level input current	V_IL = 0 V at INx or ENx	–10			μA
CMTI	Common-mode transient immunity	V_I = V_CC or 0 V; see Figure 17	25	70		kV/μs
C_I	Input capacitance⁽²⁾	V_I = V_CC/2 + 0.4 sin (2πft), f = 1 MHz, V_CC = 5 V		3.4		pF

(1) V_CCO is supply voltage, V_CC1 or V_CC2, for the output channel being measured.

(2) Measured from input pin to ground.

7.10 Supply Current Characteristics—5-V Supply

All inputs switching with square wave clock signal for dynamic I_CC measurement. V_CC1 and V_CC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS		SUPPLY CURRENT	TYP	MAX	UNIT
ISO7340-Q1
	Supply current	EN = 0 V	Disable	I_CC1	0.6	1.4	mA
		EN = 0 V	Disable	I_CC2	0.4	0.8
		DC Signal: V_I = V_CC or 0 V, AC Signal: All channels switching with square wave clock input; C_L = 15 pF	DC to 1 Mbps	I_CC1	0.6	1.4
			DC to 1 Mbps	I_CC2	3.2	4.8
			10 Mbps	I_CC1	1.4	2.3
			10 Mbps	I_CC2	5.6	7.1
			25 Mbps	I_CC1	2.7	4
			25 Mbps	I_CC2	9.3	12
ISO7341-Q1
	Supply current	EN1 = EN2 = 0 V	Disable	I_CC1	0.8	1.8	mA
		EN1 = EN2 = 0 V	Disable	I_CC2	0.7	1.3
		DC Signal: V_I = V_CC or 0 V, AC Signal: All channels switching with square wave clock input; C_L = 15 pF	DC to 1 Mbps	I_CC1	2	3.2
			DC to 1 Mbps	I_CC2	2.9	4.4
			10 Mbps	I_CC1	3.2	4.5
			10 Mbps	I_CC2	4.9	6.5
			25 Mbps	I_CC1	5	7
			25 Mbps	I_CC2	7.8	11
ISO7342-Q1
	Supply current	EN1 = EN2 = 0 V	Disable	I_CC1, I_CC2	0.7	1.6	mA
		DC Signal: V_I = V_CC or 0 V, AC Signal: All channels switching with square wave clock input; C_L = 15 pF	DC to 1 Mbps	I_CC1, I_CC2	2.5	4
			10 Mbps	I_CC1, I_CC2	4.1	5.6
			25 Mbps	I_CC1, I_CC2	6.4	9

7.11 Electrical Characteristics—3.3-V Supply

V_CC1 and V_CC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –4 mA; see Figure 14	V_CCO⁽¹⁾ – 0.5	3		V
V_OH	High-level output voltage	I_OH= –20 μA; see Figure 14	V_CCO⁽¹⁾ – 0.1	3.3		V
V_OL	Low-level output voltage	I_OL = 4 mA; see Figure 14		0.2	0.4	V
V_OL	Low-level output voltage	I_OL = 20 μA; see Figure 14		0	0.1	V
V_I(HYS)	Input threshold voltage hysteresis			450		mV
I_IH	High-level input current	V_IH = V_CC at INx or ENx			10	μA
I_IL	Low-level input current	V_IL = 0 V at INx or ENx	–10			μA
CMTI	Common-mode transient immunity	V_I = V_CC or 0 V; see Figure 17	25	50		kV/μs

(1) V_CCO is supply voltage, V_CC1 or V_CC2, for the output channel being measured.

7.12 Supply Current Characteristics—3.3-V Supply

All inputs switching with square wave clock signal for dynamic I_CC measurement. V_CC1 and V_CC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS		SUPPLY CURRENT	TYP	MAX	UNIT
ISO7340-Q1
	Supply current	EN = 0 V	Disable	I_CC1	0.4	0.7	mA
		EN = 0 V	Disable	I_CC2	0.3	0.6
		DC Signal: V_I = V_CC or 0 V, AC Signal: All channels switching with square wave clock input; C_L = 15 pF	DC to 1 Mbps	I_CC1	0.4	0.7
			DC to 1 Mbps	I_CC2	2.3	3.6
			10 Mbps	I_CC1	0.9	1.3
			10 Mbps	I_CC2	3.9	5.1
			25 Mbps	I_CC1	1.6	2.4
			25 Mbps	I_CC2	6.3	8
ISO7341-Q1
	Supply current	EN1 = EN2 = 0 V	Disable	I_CC1	0.6	1	mA
		EN1 = EN2 = 0 V	Disable	I_CC2	0.5	0.8
		DC Signal: V_I = V_CC or 0 V, AC Signal: All channels switching with square wave clock input; C_L = 15 pF	DC to 1 Mbps	I_CC1	1.4	2.3
			DC to 1 Mbps	I_CC2	2.2	3.2
			10 Mbps	I_CC1	2.2	3
			10 Mbps	I_CC2	3.4	4.5
			25 Mbps	I_CC1	3.3	4.7
			25 Mbps	I_CC2	5.2	7.2
ISO7342-Q1
	Supply current	EN1 = EN2 = 0 V	Disable	I_CC1, I_CC2	0.5	0.9	mA
		DC Signal: V_I = V_CC or 0 V, AC Signal: All channels switching with square wave clock input; C_L = 15 pF	DC to 1 Mbps	I_CC1, I_CC2	1.8	2.8
			10 Mbps	I_CC1, I_CC2	2.8	4
			25 Mbps	I_CC1, I_CC2	4.3	5.8

7.13 Switching Characteristics—5-V Supply

V_CC1 and V_CC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time		See Figure 14	20	31	58	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|		See Figure 14			4	ns
t_sk(o)⁽²⁾	Channel-to-channel output skew time		Same-direction Channels			2.5	ns
t_sk(o)⁽²⁾	Channel-to-channel output skew time		Opposite-direction Channels			17	ns
t_sk(pp)⁽³⁾	Part-to-part skew time					23	ns
t_r	Output signal rise time		See Figure 14		2.1		ns
t_f	Output signal fall time		See Figure 14		1.7		ns
t_PHZ	Disable propagation delay, high-to-high impedance output		See Figure 15		7	13	ns
t_PLZ	Disable propagation delay, low-to-high impedance output				7	13	ns
t_PZH	Enable propagation delay, high impedance-to-high output	ISO734xCQDWQ1 and ISO734xCQDWRQ1			7	13	ns
t_PZH	Enable propagation delay, high impedance-to-high output	ISO734xFCQDWQ1 and ISO734xFCQDWRQ1			15000	23000⁽⁴⁾	ns
t_PZL	Enable propagation delay, high impedance-to-low output	ISO734xCQDWQ1 and ISO734xCQDWRQ1			15000	23000⁽⁴⁾	ns
t_PZL	Enable propagation delay, high impedance-to-low output	ISO734xFCQDWQ1 and ISO734xFCQDWRQ1			7	13	ns
t_fs	Fail-safe output delay time from input power loss		See Figure 16		9.4		μs

(1) Also known as Pulse Skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.

(3) t_sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

(4) The enable signal rate should be ≤ 43 Kbps.

7.14 Switching Characteristics—3.3-V Supply

V_CC1 and V_CC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time		See Figure 14	22	35	66	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|		See Figure 14			2.5
t_sk(o) ⁽²⁾	Channel-to-channel output skew time		Same-direction Channels			3
t_sk(o) ⁽²⁾	Channel-to-channel output skew time		Opposite-direction Channels			16
t_sk(pp) ⁽³⁾	Part-to-part skew time					28
t_r	Output signal rise time		See Figure 14		2.8		ns
t_f	Output signal fall time		See Figure 14		2.1		ns
t_PHZ	Disable propagation delay, high-to-high impedance output		See Figure 15		9	18	ns
t_PLZ	Disable propagation delay, low-to-high impedance output				9	18
t_PZH	Enable propagation delay, high impedance-to-high output	ISO734xCQDWQ1 and ISO734xCQDWRQ1			9	18
t_PZH	Enable propagation delay, high impedance-to-high output	ISO734xFCQDWQ1 and ISO734xFCQDWRQ1			16000	24000⁽⁴⁾
t_PZL	Enable propagation delay, high impedance-to-low output	ISO734xCQDWQ1 and ISO734xCQDWRQ1			16000	24000⁽⁴⁾
t_PZL	Enable propagation delay, high impedance-to-low output	ISO734xFCQDWQ1 and ISO734xFCQDWRQ1			9	18
t_fs	Fail-safe output delay time from input power loss		See Figure 16		9.4		μs

(1) Also known as Pulse Skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.

(4) The enable signal rate should be ≤ 45 Kbps.