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The ISO734x family of devices provides galvanic isolation up to 3000 VRMS for 1 minute per UL 1577 and 4242 VPK per VDE V 0884-10. These devices have four isolated channels comprised of logic input and output buffers separated by a silicon dioxide (SiO2) insulation barrier.
The ISO7340x device has four channels in forward direction, the ISO7341x device has three forward and one reverse-direction channels, and the ISO7342x device has two forward and two reverse-direction channels. In case of input power or signal loss, the default output is low for devices with suffix F and high for devices without suffix F. See the Device Functional Modes section for further details.
PART NUMBER | PACKAGE | BODY SIZE |
---|---|---|
ISO7340C | SOIC (16) | 10.30 mm × 7.50 mm |
ISO7340FC | ||
ISO7341C | ||
ISO7341FC | ||
ISO7342C | ||
ISO7342FC |
Changes from F Revision (August 2016) to G Revision
Changes from E Revision (April 2015) to F Revision
Changes from D Revision (March 2015) to E Revision
Changes from C Revision (December 2014) to D Revision
Changes from B Revision (November 2014) to C Revision
Changes from A Revision (Octoberr 2014) to B Revision
Changes from * Revision (September 2014) to A Revision
Used in conjunction with isolated power supplies, these devices help prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. The ISO734x device has integrated noise filter for harsh industrial environment where short noise pulses may be present at the device input pins. The ISO734x device has TTL input thresholds and operates from 3-V to 5.5-V supply levels. Through innovative chip design and layout techniques, electromagnetic compatibility of the ISO734x family of devices has been significantly enhanced to enable system-level ESD, EFT, surge, and emissions compliance.
PIN | I/O | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | NO. | ||||
ISO7340x | ISO7341x | ISO7342x | |||
EN | 10 | — | — | I | Output enable. All output pins are enabled when EN is high or disconnected and disabled when EN is low. |
EN1 | — | 7 | 7 | I | Output enable 1. Output pins on side-1 are enabled when EN1 is high or disconnected and disabled when EN1 is low. |
EN2 | — | 10 | 10 | I | Output enable 2. Output pins on side-2 are enabled when EN2 is high or disconnected and disabled when EN2 is low. |
GND1 | 2 | 2 | 2 | — | Ground connection for VCC1 |
8 | 8 | 8 | |||
GND2 | 9 | 9 | 9 | — | Ground connection for VCC2 |
15 | 15 | 15 | |||
INA | 3 | 3 | 3 | I | Input, channel A |
INB | 4 | 4 | 4 | I | Input, channel B |
INC | 5 | 5 | 12 | I | Input, channel C |
IND | 6 | 11 | 11 | I | Input, channel D |
NC | 7 | — | — | — | No connect pins are floating with no internal connection |
OUTA | 14 | 14 | 14 | O | Output, channel A |
OUTB | 13 | 13 | 13 | O | Output, channel B |
OUTC | 12 | 12 | 5 | O | Output, channel C |
OUTD | 11 | 6 | 6 | O | Output, channel D |
VCC1 | 1 | 1 | 1 | — | Power supply, VCC1 |
VCC2 | 16 | 16 | 16 | — | Power supply, VCC2 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VCC | Supply voltage(2) | VCC1, VCC2 | –0.5 | 6 | V |
Voltage | INx, OUTx, ENx | –0.5 | VCC + 0.5(3) | V | |
IO | Output current | ±15 | mA | ||
TJ | Maximum junction temperature | 150 | °C | ||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 | V |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VCC1, VCC2 | Supply voltage | 3 | 5.5 | V | |
IOH | High-level output current | –4 | mA | ||
IOL | Low-level output current | 4 | mA | ||
VIH | High-level input voltage | 2 | 5.5 | V | |
VIL | Low-level input voltage | 0 | 0.8 | V | |
tui | Input pulse duration | 40 | ns | ||
1 / tui | Signaling rate | 0 | 25 | Mbps | |
TJ | Junction temperature(1) | 136 | °C | ||
TA | Ambient temperature | –40 | 25 | 125 | °C |
THERMAL METRIC(1) | ISO734x | UNIT | ||
---|---|---|---|---|
DW (SOIC) | ||||
16 PINS | ||||
RθJA | Junction-to-ambient thermal resistance | 78.4 | °C/W | |
RθJC(top) | Junction-to-case(top) thermal resistance | 41 | °C/W | |
RθJB | Junction-to-board thermal resistance | 43 | °C/W | |
ψJT | Junction-to-top characterization parameter | 15.6 | °C/W | |
ψJB | Junction-to-board characterization parameter | 42.5 | °C/W | |
RθJC(bottom) | Junction-to-case(bottom) thermal resistance | n/a | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PD | Maximum power dissipation by both sides of ISO7340x | 92 | mW | |||
PD1 | Maximum power dissipation by side-1 of ISO7340x | 24 | ||||
PD2 | Maximum power dissipation by side-2 of ISO7340x | 68 | ||||
PD | Maximum power dissipation by both sides of ISO7341x | 102 | mW | |||
PD1 | Maximum power dissipation by side-1 of ISO7341x | 42 | ||||
PD2 | Maximum power dissipation by side-2 of ISO7341x | 60 | ||||
PD | Maximum power dissipation by both sides of ISO7342x | 111 | mW | |||
PD1 | Maximum power dissipation by side-1 of ISO7342x | 55.5 | ||||
PD2 | Maximum power dissipation by side-2 of ISO7342x | 55.5 |
PARAMETER | TEST CONDITIONS | VALUE | UNIT | |
---|---|---|---|---|
GENERAL | ||||
CLR | External clearance(1) | Shortest terminal-to-terminal distance through air | >8 | mm |
CPG | External creepage(1) | Shortest terminal-to-terminal distance across the package surface | >8 | mm |
DTI | Distance through the insulation | Minimum internal gap (internal clearance) | >13 | µm |
CTI | Comparative tracking index | DIN EN 60112 (VDE 0303-11); IEC 60112 | >400 | V |
Material group | II | |||
Overvoltage Category | Rated mains voltage ≤ 300 VRMS | I–IV | ||
Rated mains voltage ≤ 600 VRMS | I–III | |||
Rated mains voltage ≤ 1000 VRMS | I-II | |||
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(2) | ||||
VIORM | Maximum repetitive peak isolation voltage | AC voltage (bipolar) | 1414 | VPK |
VIOTM | Maximum transient isolation voltage | VTEST = VIOTM; t = 60 s (qualification); t = 1 s (100% production) |
4242 | VPK |
VIOSM | Maximum surge isolation voltage(3) | Test method per IEC 60065, 1.2/50 µs waveform, VTEST = 1.3 × VIOSM = 7800 VPK (qualification) |
6000 | VPK |
qpd | Apparent charge(4) | Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 1697 VPK, tm = 10 s |
≤5 | pC |
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM = 2262 VPK, tm = 10 s |
≤5 | |||
Method b1: At routine test (100% production) and preconditioning (type test) Vini = VIOTM, tini = 1 s; Vpd(m) = 1.875 × VIORM = 2651 VPK, tm = 1 s (100% production) |
≤5 | |||
CIO | Barrier capacitance, input to output(5) | VIO = 0.4 sin (2πft), f = 1 MHz | 2.4 | pF |
RIO | Isolation resistance, input to output(5) | VIO = 500 V, TA = 25°C | >1012 | Ω |
VIO = 500 V, 100°C ≤ TA ≤ x°C | >1011 | |||
VIO = 500 V at TS = 150°C | >109 | |||
Pollution degree | 2 | |||
Climatic category | 40/125/21 | |||
UL 1577 | ||||
VISO | Withstand isolation voltage | VTEST = VISO = 3000 VRMS, t = 60 s (qualification); VTEST = 1.2 × VISO = 3600 VRMS, t = 1 s (100% production) | 3000 | VRMS |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
IS | Safety input, output, or supply current | RθJA = 78.4 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 1 | 290 | mA | ||
RθJA = 78.4 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 1 | 443 | |||||
TS | Safety temperature | 150 |
The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 14 | VCCO(1) – 0.5 | 4.7 | V | |
IOH = –20 μA; see Figure 14 | VCCO(1) – 0.1 | 5 | ||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 14 | 0.2 | 0.4 | V | |
IOL = 20 μA; see Figure 14 | 0 | 0.1 | ||||
VI(HYS) | Input threshold voltage hysteresis | 480 | mV | |||
IIH | High-level input current | VIH = VCC at INx or ENx | 10 | μA | ||
IIL | Low-level input current | VIL = 0 V at INx or ENx | –10 | μA | ||
CMTI | Common-mode transient immunity | VI = VCC or 0 V; see Figure 17 | 25 | 70 | kV/μs | |
CI | Input capacitance(2) | VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V | 3.4 | pF |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 14 | VCCO(1) – 0.5 | 3 | V | |
IOH = –20 μA; see Figure 14 | VCCO(1) – 0.1 | 3.3 | ||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 14 | 0.2 | 0.4 | V | |
IOL = 20 μA; see Figure 14 | 0 | 0.1 | ||||
VI(HYS) | Input threshold voltage hysteresis | 450 | mV | |||
IIH | High-level input current | VIH = VCC at INx or ENx | 10 | μA | ||
IIL | Low-level input current | VIL = 0 V at INx or ENx | –10 | μA | ||
CMTI | Common-mode transient immunity | VI = VCC or 0 V; see Figure 17 | 25 | 50 | kV/μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 14 | 20 | 31 | 58 | ns | |
PWD(1) | Pulse width distortion |tPHL – tPLH| | 4 | ns | ||||
tsk(o)(2) | Channel-to-channel output skew time | Same-direction Channels | 2.5 | ns | |||
Opposite-direction Channels | 17 | ns | |||||
tsk(pp)(3) | Part-to-part skew time | 23 | ns | ||||
tr | Output signal rise time | See Figure 14 | 2.1 | ns | |||
tf | Output signal fall time | 1.7 | ns | ||||
tPHZ | Disable propagation delay, high-to-high impedance output | See Figure 15 | 7 | 13 | ns | ||
tPLZ | Disable propagation delay, low-to-high impedance output | 7 | 13 | ns | |||
tPZH | Enable propagation delay, high impedance-to-high output | ISO734xC | 7 | 13 | ns | ||
ISO734xFC | 15000 | 23000(4) | |||||
tPZL | Enable propagation delay, high impedance-to-low output | ISO734xC | 15000 | 23000(4) | ns | ||
ISO734xFC | 7 | 13 | |||||
tfs | Fail-safe output delay time from input power loss | See Figure 16 | 9.4 | μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 14 | 22 | 35 | 66 | ns | |
PWD(1) | Pulse width distortion |tPHL – tPLH| | 2.5 | |||||
tsk(o) (2) | Channel-to-channel output skew time | Same-direction Channels | 3 | ||||
Opposite-direction Channels | 16 | ||||||
tsk(pp) (3) | Part-to-part skew time | 28 | |||||
tr | Output signal rise time | See Figure 14 | 2.8 | ns | |||
tf | Output signal fall time | 2.1 | |||||
tPHZ | Disable propagation delay, high-to-high impedance output | See Figure 15 | 9 | 18 | ns | ||
tPLZ | Disable propagation delay, low-to-high impedance output | 9 | 18 | ||||
tPZH | Enable propagation delay, high impedance-to-high output | ISO734xC | 9 | 18 | |||
ISO734xFC | 16000 | 24000(4) | |||||
tPZL | Enable propagation delay, high impedance-to-low output | ISO734xC | 16000 | 24000(4) | |||
ISO734xFC | 9 | 18 | |||||
tfs | Fail-safe output delay time from input power loss | See Figure 16 | 9.4 | μs |
TA = 25°C | CL = 15 pF |
TA = 25°C |
TA = 25°C | CL = No Load |
TA = 25°C | CL = No Load |
TA = 25°C |
TA = 25°C |