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ISO742x provide galvanic isolation up to 2500 VRMS for 1 minute per UL and 4242 VPK per VDE. These devices have two isolated channels. Each channel has a logic input and output buffer separated by a silicon dioxide (SiO2) insulation barrier. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuit from entering the local ground and interfering with or damaging sensitive circuitry. ISO7420 has both channels in the same direction while ISO7421 has the two channels in opposite direction. In case of input power or signal loss, default output is 'low' for devices with suffix 'F' and 'high' for devices without suffix 'F'. ISO742x have no integrated noise filter and thus have fast propagation delays.
These devices have TTL input thresholds and operate from 3-V to 5.5-V supplies. All inputs are 5-V tolerant when supplied from a 3.3-V supply.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ISO7420E | SOIC (8) | 4.90 mm x 3.91 mm |
ISO7420FE | ||
ISO7421E | ||
ISO7421FE |
Changes from E Revision (January 2013) to F Revision
Changes from D Revision (December 2011) to E Revision
Changes from C Revision (March 2011) to D Revision
Changes from B Revision (January 2011) to C Revision
Changes from A Revision (December 2010) to B Revision
Changes from * Revision (December 2010) to A Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | ISO7420x | ISO7421x | ||
INA | 2 | 7 | I | Input, channel A |
INB | 3 | 3 | I | Input, channel B |
GND1 | 4 | 4 | – | Ground connection for VCC1 |
GND2 | 5 | 5 | – | Ground connection for VCC2 |
OUTA | 7 | 2 | O | Output, channel A |
OUTB | 6 | 6 | O | Output, channel B |
VCC1 | 1 | 1 | – | Power supply, VCC1 |
VCC2 | 8 | 8 | – | Power supply, VCC2 |
MIN | MAX | UNIT | |||||
---|---|---|---|---|---|---|---|
VCC | Supply voltage(2), VCC1, VCC2 | –0.5 | 6 | V | |||
VI | Voltage at IN, OUT | –0.5 | VCC + 0.5(3) | V | |||
IO | Output current | ±15 | mA | ||||
VSRG | Maximum surge immunity - Supports IEC 61000-4-5 | 4000 | VPK | ||||
TJ(Max) | Maximum junction temperature | 150 | °C | ||||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±3000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 | |||
Machine model (MM) ANSI/ESDS5.2-1996 | ±200 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC1, VCC2 | Supply voltage | 3.0 | 5.5 | V | ||
IOH | High-level output current | –4 | mA | |||
IOL | Low-level output current | 4 | mA | |||
VIH | High-level input voltage | 2 | 5.5 | V | ||
VIL | Low-level input voltage | 0 | 0.8 | V | ||
tui | Input pulse duration | 20 | ns | |||
1 / tui | Signaling rate | 0 | 50(2) | Mbps | ||
TJ(1) | Junction temperature | –40 | 136 | °C | ||
TA | Ambient Temperature | -40 | 25 | 125 | °C |
THERMAL METRIC(1) | ISO742x | UNIT | ||
---|---|---|---|---|
D (SOIC) | ||||
8 PINS | ||||
RθJA | Junction-to-ambient thermal resistance | Low-K board | 212 | °C/W |
High-K board | 116.6 | |||
RθJC(top) | Junction-to-case (top) thermal resistance | 71.6 | °C/W | |
RθJB | Junction-to-board thermal resistance | 57.3 | °C/W | |
ψJT | Junction-to-top characterization parameter | 28.3 | °C/W | |
ψJB | Junction-to-board characterization parameter | 56.8 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 16. | VCCO(1)– 0.8 | 4.6 | V | ||
IOH = –20 μA; see Figure 16. | VCCO– 0.1 | 5 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 16. | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 16. | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 400 | mV | ||||
IIH | High-level input current | INx at 0 V or VCCI(1) | 10 | μA | |||
IIL | Low-level input current | –10 | μA | ||||
CMTI | Common-mode transient immunity | VI = VCCI or 0 V; see Figure 18. | 25 | 50 | kV/μs | ||
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) | |||||||
ISO7420x | |||||||
ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCCI or 0 V, AC Input: CL = 15 pF |
0.4 | 0.8 | mA | |
ICC2 | 3.4 | 5 | |||||
ICC1 | 10 Mbps | CL = 15 pF | 0.6 | 1 | |||
ICC2 | 4.5 | 6 | |||||
ICC1 | 25 Mbps | 1 | 1.5 | ||||
ICC2 | 6.2 | 8 | |||||
ICC1 | 50 Mbps | 1.7 | 2.5 | ||||
ICC2 | 9 | 12 | |||||
ISO7421x | |||||||
ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCCI or 0 V, AC Input: CL = 15 pF |
2.3 | 3.6 | mA | |
ICC2 | 2.3 | 3.6 | |||||
ICC1 | 10 Mbps | CL = 15 pF | 2.9 | 4.5 | |||
ICC2 | 2.9 | 4.5 | |||||
ICC1 | 25 Mbps | 4.3 | 6 | ||||
ICC2 | 4.3 | 6 | |||||
ICC1 | 50 Mbps | 6 | 8.5 | ||||
ICC2 | 6 | 8.5 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 16. | ISO7421x (5-V side) | VCC1 – 0.8 | 4.6 | V | |
ISO7420x/7421x (3.3-V side) | VCC2 - 0.4 | 3 | |||||
IOH = –20 μA; see Figure 16, | ISO7421x (5-V side) | VCC1 – 0.1 | 5 | ||||
ISO7420x/7421x (3.3-V side) | VCC2 – 0.1 | 3.3 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 16. | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 16. | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 400 | mV | ||||
IIH | High-level input current | INx at 0 V or VCCI | 10 | μA | |||
IIL | Low-level input current | –10 | μA | ||||
CMTI | Common-mode transient immunity | VI = VCCI or 0 V; see Figure 18. | 25 | 50 | kV/μs | ||
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) | |||||||
ISO7420x | |||||||
ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCCI or 0 V, AC Input: CL = 15 pF |
0.4 | 0.8 | mA | |
ICC2 | 2.6 | 3.7 | |||||
ICC1 | 10 Mbps | CL = 15 pF | 0.6 | 1 | |||
ICC2 | 3.3 | 4.3 | |||||
ICC1 | 25 Mbps | 1 | 1.5 | ||||
ICC2 | 4.4 | 5.6 | |||||
ICC1 | 50 Mbps | 1.7 | 2.5 | ||||
ICC2 | 6.2 | 7.5 | |||||
ISO7421x | |||||||
ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCCI or 0 V, AC Input: CL = 15 pF |
2.3 | 3.6 | mA | |
ICC2 | 1.8 | 2.8 | |||||
ICC1 | 10 Mbps | CL = 15 pF | 2.9 | 4.5 | |||
ICC2 | 2.2 | 3.2 | |||||
ICC1 | 25 Mbps | 4.3 | 6 | ||||
ICC2 | 2.8 | 4.1 | |||||
ICC1 | 50 Mbps | 6 | 8.5 | ||||
ICC2 | 3.8 | 5.5 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 16. | ISO7421x (3.3-V side) | VCC1 – 0.4 | 3 | V | |
ISO7420x/7421x (5-V side) | VCC2 – 0.8 | 4.6 | |||||
IOH = –20 μA; see Figure 16 | ISO7421x (3.3-V side) | VCC1 – 0.1 | 3.3 | ||||
ISO7420x/7421x (5-V side) | VCC2 – 0.1 | 5 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 16. | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 16. | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 400 | mV | ||||
IIH | High-level input current | INx at 0 V or VCCI | 10 | μA | |||
IIL | Low-level input current | –10 | μA | ||||
CMTI | Common-mode transient immunity | VI = VCCI or 0 V; see Figure 18. | 25 | 50 | kV/μs | ||
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) | |||||||
ISO7420x | |||||||
ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCCI or 0 V, AC Input: CL = 15 pF |
0.2 | 0.4 | mA | |
ICC2 | 3.4 | 5 | |||||
ICC1 | 10 Mbps | CL = 15 pF | 0.4 | 0.6 | |||
ICC2 | 4.5 | 6 | |||||
ICC1 | 25 Mbps | 0.6 | 0.9 | ||||
ICC2 | 6.2 | 8 | |||||
ICC1 | 50 Mbps | 1 | 1.3 | ||||
ICC2 | 9 | 12 | |||||
ISO7421x | |||||||
ICC1 | Supply current for VCC2 and VCC2 | DC to 1 Mbps | DC Input: VI = VCCI or 0 V, AC Input: CL = 15 pF |
1.8 | 2.8 | mA | |
ICC2 | 2.3 | 3.6 | |||||
ICC1 | 10 Mbps | CL = 15 pF | 2.2 | 3.2 | |||
ICC2 | 2.9 | 4.5 | |||||
ICC1 | 25 Mbps | 2.8 | 4.1 | ||||
ICC2 | 4.3 | 6 | |||||
ICC1 | 50 Mbps | 3.8 | 5.5 | ||||
ICC2 | 6 | 8.5 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 16. | VCCO(1) – 0.4 | 3 | V | ||
IOH = –20 μA; see Figure 16. | VCCO – 0.1 | 3.3 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 16. | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 16. | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 400 | mV | ||||
IIH | High-level input current | INx at 0 V or VCCI(1) | 10 | μA | |||
IIL | Low-level input current | –10 | μA | ||||
CMTI | Common-mode transient immunity | VI = VCCI or 0 V; see Figure 18. | 25 | 50 | kV/μs | ||
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) | |||||||
ISO7420x | |||||||
ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCCI or 0 V, AC Input: CL = 15 pF |
0.2 | 0.4 | mA | |
ICC2 | 2.6 | 3.7 | |||||
ICC1 | 10 Mbps | CL = 15 pF | 0.4 | 0.6 | |||
ICC2 | 3.3 | 4.3 | |||||
ICC1 | 25 Mbps | 0.6 | 0.9 | ||||
ICC2 | 4.4 | 5.6 | |||||
ICC1 | 50 Mbps | 1 | 1.3 | ||||
ICC2 | 6.2 | 7.5 | |||||
ISO7421x | |||||||
ICC1 | Supply current for VCC2 and VCC2 | DC to 1 Mbps | DC Input: VI = VCCI or 0 V, AC Input: CL = 15 pF |
1.8 | 2.8 | mA | |
ICC2 | 1.8 | 2.8 | |||||
ICC1 | 10 Mbps | CL = 15 pF | 2.2 | 3.2 | |||
ICC2 | 2.2 | 3.2 | |||||
ICC1 | 25 Mbps | 2.8 | 4.1 | ||||
ICC2 | 2.8 | 4.1 | |||||
ICC1 | 50 Mbps | 3.8 | 5.5 | ||||
ICC2 | 3.8 | 5.5 |
THERMAL METRIC | ISO742x | UNIT | ||
---|---|---|---|---|
D (SOIC) | ||||
8 PINS | ||||
PD | Device power dissipation | VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 100-Mbps 50% duty-cycle square wave |
138 | mW |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 16. | 7 | 11 | ns | ||
PWD(1) | Pulse width distortion |tPHL – tPLH| | ISO7420x | 0.2 | 3 | ns | ||
ISO7421x | 0.3 | 3.7 | |||||
tsk(o)(2) | Channel-to-channel output skew time | ISO7420x | 0.3 | 1 | ns | ||
ISO7421x | 0.3 | 2 | |||||
tsk(pp)(3) | Part-to-part skew time | ISO7420x | 3.7 | ns | |||
ISO7421x | 4.9 | ||||||
tr | Output signal rise time | See Figure 16. | 1.8 | ns | |||
tf | Output signal fall time | 1.7 | ns | ||||
tfs | Fail-safe output delay time from input power loss | See Figure 17. | 6 | μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 16. | 8 | 13.5 | ns | ||
PWD(1) | Pulse width distortion |tPHL – tPLH| | ISO7420x | 0.3 | 3 | ns | ||
ISO7421x | 0.5 | 5.6 | |||||
tsk(o)(2) | Channel-to-channel output skew time | ISO7420x | 1.5 | ns | |||
ISO7421x | 0.5 | 3 | |||||
tsk(pp)(3) | Part-to-part skew time | ISO7420x | 5.4 | ns | |||
ISO7421x | 6.3 | ||||||
tr | Output signal rise time | See Figure 16. | 2 | ns | |||
tf | Output signal fall time | 2 | ns | ||||
tfs | Fail-safe output delay time from input power loss | See Figure 17. | 6 | μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | ISO7420x | See Figure 16. | 7.5 | 12 | ns | ||
ISO7421x | 7.5 | 14 | ||||||
PWD(1) | Pulse width distortion |tPHL – tPLH| | ISO7420x | 0.7 | 3 | ns | |||
ISO7421x | 0.7 | 3.6 | ||||||
tsk(o)(2) | Channel-to-channel output skew time | ISO7420x | 0.5 | 1.5 | ns | |||
ISO7421x | 0.5 | 3 | ||||||
tsk(pp)(3) | Part-to-part skew time | ISO7420x | 4.6 | ns | ||||
ISO7421x | 8.5 | |||||||
tr | Output signal rise time | See Figure 16. | 1.7 | ns | ||||
tf | Output signal fall time | 1.6 | ns | |||||
tfs | Fail-safe output delay time from input power loss | See Figure 17. | 6 | μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 16 | 8.5 | 14 | ns | ||
PWD(1) | Pulse width distortion |tPHL – tPLH| | ISO7420x and ISO7421x | 0.5 | 2 | ns | ||
tsk(o)(2) | Channel-to-channel output skew time | ISO7420x | 0.4 | 2 | ns | ||
ISO7421x | 0.4 | 3 | |||||
tsk(pp)(3) | Part-to-part skew time | ISO7420x | 6.2 | ns | |||
ISO7421x | 6.8 | ||||||
tr | Output signal rise time | See Figure 16 | 2 | ns | |||
tf | Output signal fall time | 1.8 | ns | ||||
tfs | Fail-safe output delay time from input power loss | See Figure 17 | 6 | μs |
The isolator in Figure 19 is based on a capacitive isolation barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to
150 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a single- ended input signal entering the HF-channel is split into a differential signal via the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the low-frequency channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer.
ISO742x are available in multiple channel configurations and default output state options to enable wide variety of application uses.
PRODUCT | DATA RATE | DEFAULT OUTPUT | RATED TA | CHANNEL DIRECTION |
---|---|---|---|---|
ISO7420E | 50 Mbps | High | –40°C to 125°C | Same |
ISO7420FE | Low | |||
ISO7421E | High | Opposite | ||
ISO7421FE | Low |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
L(I01) | Minimum air gap (clearance) | Shortest terminal-to-terminal distance through air | 4 | mm | |||
L(I02) | Minimum external tracking (creepage) | Shortest terminal-to-terminal distance across the package surface | 4 | mm | |||
CTI | Tracking resistance (comparative tracking index) | DIN EN 60112 (VDE 0303-11); IEC 60112 | >400 | V | |||
Minimum internal gap (internal clearance) | Distance through the insulation | 0.014 | mm | ||||
RIO | Isolation resistance, input to output(1) | VIO = 500 V, TA = 25°C | >1012 | Ω | |||
VIO = 500 V, 100°C ≤ TA ≤ max | >1011 | Ω | |||||
CIO | Barrier capacitance, input to output(1) | VIO = 0.4 sin (2πft), f = 1 MHz | 1 | pF | |||
CI | Input capacitance(2) | VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V | 1 | pF |
NOTE
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
PARAMETER(1) | TEST CONDITIONS | SPECIFICATION | UNIT | |
---|---|---|---|---|
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 | ||||
VIORM | Maximum workingisolation voltage | 566 | VPEAK | |
VPR | Input-to-output test voltage | Method a, After environmental tests subgroup 1, VPR = VIORM x 1.6, t = 10 s, Partial Discharge < 5 pC |
906 | VPEAK |
Method b1, VPR = VIORM x 1.875, t = 1 s (100% Production test) Partial discharge < 5 pC |
1062 | |||
After Input/Output safety test subgroup 2/3, VPR = VIORM x 1.2, t = 10 s, Partial discharge < 5 pC |
680 | |||
VIOTM | Maximum transient isolation voltage | VTEST = VIOTM = 4242 VPK
t = 60 sec (qualification) t= 1 sec (100% production) |
4242 | VPEAK |
RS | Isolation resistance | VIO = 500 V at TS = 150°C | >109 | Ω |
Pollution degree | 2 | |||
UL 1577 | ||||
VISO | Maximum withstand isolation voltage | VTEST = VISO = 2500 VRMS, t = 60 sec (qualification); VTEST = 1.2 x VISO = 3000 VRMS, t = 1 sec (100% production) |
2500 | VRMS |
PARAMETER | TEST CONDITIONS | SPECIFICATION |
---|---|---|
Basic isolation group | Material group | II |
Installation classification | Rated mains voltage ≤ 150 VRMS | I–IV |
Rated mains voltage ≤ 300 VRMS | I–III |
VDE | CSA | UL | CQC |
---|---|---|---|
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 61010-1 (VDE 0411-1):2011-07 | Approved under CSA Component Acceptance Notice 5A, IEC 60950-1, and IEC 61010-1 | Recognized under UL 1577 Component Recognition Program | Certified according to GB 4943.1-2011 |
Basic Insulation; Maximum Transient Isolation Voltage, 4242 VPK; Maximum Working Isolation Voltage, 566 VPK |
2500 VRMS Isolation Rating; Basic insulation per CSA 60950-1-07+A1 and IEC 60950-1 2nd Ed+A1, 384 VRMS maximum working voltage; CSA 61010-1-04 and IEC 61010-1 2nd Ed, 300 VRMS maximum working voltage for basic insulation and 150 VRMS for reinforced insulation |
Single Protection Isolation Voltage, 2500 VRMS(1) | Basic Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS maximum working voltage |
Certificate number: 40016131 | Master contract number: 220991 | File number: E181974 | Certificate number: CQC14001109540 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
IS | Safety input, output, or supply current | θJA = 212°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C | 107 | mA | ||
θJA = 212°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C | 164 | |||||
TS | Maximum safety temperature | 150 | °C |
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed in the JESD51-3, Low-Effective-Thermal-Conductivity Test Board for Leaded Surface-Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.
VCCI | VCCO | INPUT INA, INB |
OUTPUT OUTA, OUTB |
|
---|---|---|---|---|
ISO7420E / ISO7421E | ISO7420FE / ISO7421FE | |||
PU | PU | H | H | H |
L | L | L | ||
Open | H(2) | L(3) | ||
PD | PU | X | H(2) | L(3) |
X | PD | X | Undetermined | Undetermined |