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ISO742x provide galvanic isolation up to 2500 VRMS for 1 minute per UL and 4242 VPK per VDE. These devices have two isolated channels. Each channel has a logic input and output buffer separated by a silicon dioxide (SiO2) insulation barrier. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuit from entering the local ground and interfering with or damaging sensitive circuitry. ISO7420 has both channels in the same direction while ISO7421 has the two channels in opposite direction. In case of input power or signal loss, default output is 'low' for devices with suffix 'F' and 'high' for devices without suffix 'F'. ISO742x have no integrated noise filter and thus have fast propagation delays.
These devices have TTL input thresholds and operate from 3-V to 5.5-V supplies. All inputs are 5-V tolerant when supplied from a 3.3-V supply.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ISO7420E | SOIC (8) | 4.90 mm x 3.91 mm |
ISO7420FE | ||
ISO7421E | ||
ISO7421FE |
Changes from E Revision (January 2013) to F Revision
Changes from D Revision (December 2011) to E Revision
Changes from C Revision (March 2011) to D Revision
Changes from B Revision (January 2011) to C Revision
Changes from A Revision (December 2010) to B Revision
Changes from * Revision (December 2010) to A Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | ISO7420x | ISO7421x | ||
INA | 2 | 7 | I | Input, channel A |
INB | 3 | 3 | I | Input, channel B |
GND1 | 4 | 4 | – | Ground connection for VCC1 |
GND2 | 5 | 5 | – | Ground connection for VCC2 |
OUTA | 7 | 2 | O | Output, channel A |
OUTB | 6 | 6 | O | Output, channel B |
VCC1 | 1 | 1 | – | Power supply, VCC1 |
VCC2 | 8 | 8 | – | Power supply, VCC2 |
MIN | MAX | UNIT | |||||
---|---|---|---|---|---|---|---|
VCC | Supply voltage(2), VCC1, VCC2 | –0.5 | 6 | V | |||
VI | Voltage at IN, OUT | –0.5 | VCC + 0.5(3) | V | |||
IO | Output current | ±15 | mA | ||||
VSRG | Maximum surge immunity - Supports IEC 61000-4-5 | 4000 | VPK | ||||
TJ(Max) | Maximum junction temperature | 150 | °C | ||||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±3000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 | |||
Machine model (MM) ANSI/ESDS5.2-1996 | ±200 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC1, VCC2 | Supply voltage | 3.0 | 5.5 | V | ||
IOH | High-level output current | –4 | mA | |||
IOL | Low-level output current | 4 | mA | |||
VIH | High-level input voltage | 2 | 5.5 | V | ||
VIL | Low-level input voltage | 0 | 0.8 | V | ||
tui | Input pulse duration | 20 | ns | |||
1 / tui | Signaling rate | 0 | 50(2) | Mbps | ||
TJ(1) | Junction temperature | –40 | 136 | °C | ||
TA | Ambient Temperature | -40 | 25 | 125 | °C |
THERMAL METRIC(1) | ISO742x | UNIT | ||
---|---|---|---|---|
D (SOIC) | ||||
8 PINS | ||||
RθJA | Junction-to-ambient thermal resistance | Low-K board | 212 | °C/W |
High-K board | 116.6 | |||
RθJC(top) | Junction-to-case (top) thermal resistance | 71.6 | °C/W | |
RθJB | Junction-to-board thermal resistance | 57.3 | °C/W | |
ψJT | Junction-to-top characterization parameter | 28.3 | °C/W | |
ψJB | Junction-to-board characterization parameter | 56.8 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 16. | VCCO(1)– 0.8 | 4.6 | V | ||
IOH = –20 μA; see Figure 16. | VCCO– 0.1 | 5 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 16. | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 16. | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 400 | mV | ||||
IIH | High-level input current | INx at 0 V or VCCI(1) | 10 | μA | |||
IIL | Low-level input current | –10 | μA | ||||
CMTI | Common-mode transient immunity | VI = VCCI or 0 V; see Figure 18. | 25 | 50 | kV/μs | ||
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) | |||||||
ISO7420x | |||||||
ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCCI or 0 V, AC Input: CL = 15 pF |
0.4 | 0.8 | mA | |
ICC2 | 3.4 | 5 | |||||
ICC1 | 10 Mbps | CL = 15 pF | 0.6 | 1 | |||
ICC2 | 4.5 | 6 | |||||
ICC1 | 25 Mbps | 1 | 1.5 | ||||
ICC2 | 6.2 | 8 | |||||
ICC1 | 50 Mbps | 1.7 | 2.5 | ||||
ICC2 | 9 | 12 | |||||
ISO7421x | |||||||
ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCCI or 0 V, AC Input: CL = 15 pF |
2.3 | 3.6 | mA | |
ICC2 | 2.3 | 3.6 | |||||
ICC1 | 10 Mbps | CL = 15 pF | 2.9 | 4.5 | |||
ICC2 | 2.9 | 4.5 | |||||
ICC1 | 25 Mbps | 4.3 | 6 | ||||
ICC2 | 4.3 | 6 | |||||
ICC1 | 50 Mbps | 6 | 8.5 | ||||
ICC2 | 6 | 8.5 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 16. | ISO7421x (5-V side) | VCC1 – 0.8 | 4.6 | V | |
ISO7420x/7421x (3.3-V side) | VCC2 - 0.4 | 3 | |||||
IOH = –20 μA; see Figure 16, | ISO7421x (5-V side) | VCC1 – 0.1 | 5 | ||||
ISO7420x/7421x (3.3-V side) | VCC2 – 0.1 | 3.3 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 16. | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 16. | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 400 | mV | ||||
IIH | High-level input current | INx at 0 V or VCCI | 10 | μA | |||
IIL | Low-level input current | –10 | μA | ||||
CMTI | Common-mode transient immunity | VI = VCCI or 0 V; see Figure 18. | 25 | 50 | kV/μs | ||
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) | |||||||
ISO7420x | |||||||
ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCCI or 0 V, AC Input: CL = 15 pF |
0.4 | 0.8 | mA | |
ICC2 | 2.6 | 3.7 | |||||
ICC1 | 10 Mbps | CL = 15 pF | 0.6 | 1 | |||
ICC2 | 3.3 | 4.3 | |||||
ICC1 | 25 Mbps | 1 | 1.5 | ||||
ICC2 | 4.4 | 5.6 | |||||
ICC1 | 50 Mbps | 1.7 | 2.5 | ||||
ICC2 | 6.2 | 7.5 | |||||
ISO7421x | |||||||
ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCCI or 0 V, AC Input: CL = 15 pF |
2.3 | 3.6 | mA | |
ICC2 | 1.8 | 2.8 | |||||
ICC1 | 10 Mbps | CL = 15 pF | 2.9 | 4.5 | |||
ICC2 | 2.2 | 3.2 | |||||
ICC1 | 25 Mbps | 4.3 | 6 | ||||
ICC2 | 2.8 | 4.1 | |||||
ICC1 | 50 Mbps | 6 | 8.5 | ||||
ICC2 | 3.8 | 5.5 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 16. | ISO7421x (3.3-V side) | VCC1 – 0.4 | 3 | V | |
ISO7420x/7421x (5-V side) | VCC2 – 0.8 | 4.6 | |||||
IOH = –20 μA; see Figure 16 | ISO7421x (3.3-V side) | VCC1 – 0.1 | 3.3 | ||||
ISO7420x/7421x (5-V side) | VCC2 – 0.1 | 5 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 16. | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 16. | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 400 | mV | ||||
IIH | High-level input current | INx at 0 V or VCCI | 10 | μA | |||
IIL | Low-level input current | –10 | μA | ||||
CMTI | Common-mode transient immunity | VI = VCCI or 0 V; see Figure 18. | 25 | 50 | kV/μs | ||
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) | |||||||
ISO7420x | |||||||
ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCCI or 0 V, AC Input: CL = 15 pF |
0.2 | 0.4 | mA | |
ICC2 | 3.4 | 5 | |||||
ICC1 | 10 Mbps | CL = 15 pF | 0.4 | 0.6 | |||
ICC2 | 4.5 | 6 | |||||
ICC1 | 25 Mbps | 0.6 | 0.9 | ||||
ICC2 | 6.2 | 8 | |||||
ICC1 | 50 Mbps | 1 | 1.3 | ||||
ICC2 | 9 | 12 | |||||
ISO7421x | |||||||
ICC1 | Supply current for VCC2 and VCC2 | DC to 1 Mbps | DC Input: VI = VCCI or 0 V, AC Input: CL = 15 pF |
1.8 | 2.8 | mA | |
ICC2 | 2.3 | 3.6 | |||||
ICC1 | 10 Mbps | CL = 15 pF | 2.2 | 3.2 | |||
ICC2 | 2.9 | 4.5 | |||||
ICC1 | 25 Mbps | 2.8 | 4.1 | ||||
ICC2 | 4.3 | 6 | |||||
ICC1 | 50 Mbps | 3.8 | 5.5 | ||||
ICC2 | 6 | 8.5 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 16. | VCCO(1) – 0.4 | 3 | V | ||
IOH = –20 μA; see Figure 16. | VCCO – 0.1 | 3.3 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 16. | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 16. | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 400 | mV | ||||
IIH | High-level input current | INx at 0 V or VCCI(1) | 10 | μA | |||
IIL | Low-level input current | –10 | μA | ||||
CMTI | Common-mode transient immunity | VI = VCCI or 0 V; see Figure 18. | 25 | 50 | kV/μs | ||
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) | |||||||
ISO7420x | |||||||
ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCCI or 0 V, AC Input: CL = 15 pF |
0.2 | 0.4 | mA | |
ICC2 | 2.6 | 3.7 | |||||
ICC1 | 10 Mbps | CL = 15 pF | 0.4 | 0.6 | |||
ICC2 | 3.3 | 4.3 | |||||
ICC1 | 25 Mbps | 0.6 | 0.9 | ||||
ICC2 | 4.4 | 5.6 | |||||
ICC1 | 50 Mbps | 1 | 1.3 | ||||
ICC2 | 6.2 | 7.5 | |||||
ISO7421x | |||||||
ICC1 | Supply current for VCC2 and VCC2 | DC to 1 Mbps | DC Input: VI = VCCI or 0 V, AC Input: CL = 15 pF |
1.8 | 2.8 | mA | |
ICC2 | 1.8 | 2.8 | |||||
ICC1 | 10 Mbps | CL = 15 pF | 2.2 | 3.2 | |||
ICC2 | 2.2 | 3.2 | |||||
ICC1 | 25 Mbps | 2.8 | 4.1 | ||||
ICC2 | 2.8 | 4.1 | |||||
ICC1 | 50 Mbps | 3.8 | 5.5 | ||||
ICC2 | 3.8 | 5.5 |
THERMAL METRIC | ISO742x | UNIT | ||
---|---|---|---|---|
D (SOIC) | ||||
8 PINS | ||||
PD | Device power dissipation | VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 100-Mbps 50% duty-cycle square wave |
138 | mW |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 16. | 7 | 11 | ns | ||
PWD(1) | Pulse width distortion |tPHL – tPLH| | ISO7420x | 0.2 | 3 | ns | ||
ISO7421x | 0.3 | 3.7 | |||||
tsk(o)(2) | Channel-to-channel output skew time | ISO7420x | 0.3 | 1 | ns | ||
ISO7421x | 0.3 | 2 | |||||
tsk(pp)(3) | Part-to-part skew time | ISO7420x | 3.7 | ns | |||
ISO7421x | 4.9 | ||||||
tr | Output signal rise time | See Figure 16. | 1.8 | ns | |||
tf | Output signal fall time | 1.7 | ns | ||||
tfs | Fail-safe output delay time from input power loss | See Figure 17. | 6 | μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 16. | 8 | 13.5 | ns | ||
PWD(1) | Pulse width distortion |tPHL – tPLH| | ISO7420x | 0.3 | 3 | ns | ||
ISO7421x | 0.5 | 5.6 | |||||
tsk(o)(2) | Channel-to-channel output skew time | ISO7420x | 1.5 | ns | |||
ISO7421x | 0.5 | 3 | |||||
tsk(pp)(3) | Part-to-part skew time | ISO7420x | 5.4 | ns | |||
ISO7421x | 6.3 | ||||||
tr | Output signal rise time | See Figure 16. | 2 | ns | |||
tf | Output signal fall time | 2 | ns | ||||
tfs | Fail-safe output delay time from input power loss | See Figure 17. | 6 | μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | ISO7420x | See Figure 16. | 7.5 | 12 | ns | ||
ISO7421x | 7.5 | 14 | ||||||
PWD(1) | Pulse width distortion |tPHL – tPLH| | ISO7420x | 0.7 | 3 | ns | |||
ISO7421x | 0.7 | 3.6 | ||||||
tsk(o)(2) | Channel-to-channel output skew time | ISO7420x | 0.5 | 1.5 | ns | |||
ISO7421x | 0.5 | 3 | ||||||
tsk(pp)(3) | Part-to-part skew time | ISO7420x | 4.6 | ns | ||||
ISO7421x | 8.5 | |||||||
tr | Output signal rise time | See Figure 16. | 1.7 | ns | ||||
tf | Output signal fall time | 1.6 | ns | |||||
tfs | Fail-safe output delay time from input power loss | See Figure 17. | 6 | μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 16 | 8.5 | 14 | ns | ||
PWD(1) | Pulse width distortion |tPHL – tPLH| | ISO7420x and ISO7421x | 0.5 | 2 | ns | ||
tsk(o)(2) | Channel-to-channel output skew time | ISO7420x | 0.4 | 2 | ns | ||
ISO7421x | 0.4 | 3 | |||||
tsk(pp)(3) | Part-to-part skew time | ISO7420x | 6.2 | ns | |||
ISO7421x | 6.8 | ||||||
tr | Output signal rise time | See Figure 16 | 2 | ns | |||
tf | Output signal fall time | 1.8 | ns | ||||
tfs | Fail-safe output delay time from input power loss | See Figure 17 | 6 | μs |