SLLSE45F December   2010  – July 2015 ISO7420E , ISO7420FE , ISO7421E , ISO7421FE

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: VCC1 and VCC2 = 5 V ± 10%
    6. 6.6  Electrical Characteristics: VCC1 = 5 V ± 10%, VCC2 = 3.3 V ± 10%
    7. 6.7  Electrical Characteristics: VCC1 = 3.3 V ± 10%, VCC2 = 5 V ± 10%
    8. 6.8  Electrical Characteristics: VCC1 and VCC2 = 3.3 V ± 10%
    9. 6.9  Power Dissipation Characteristics
    10. 6.10 Switching Characteristics: VCC1 and VCC2 = 5 V ± 10%
    11. 6.11 Switching Characteristics: VCC1 = 5 V ± 10%, VCC2 = 3.3 V ± 10%
    12. 6.12 Switching Characteristics: VCC1 = 3.3 V ± 10%, VCC2 = 5 V ± 10%
    13. 6.13 Switching Characteristics: VCC1 and VCC2 = 3.3 V ± 10%
    14. 6.14 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Insulation and Safety-Related Specifications for D-8 Package
      2. 8.3.2 Insulation Characteristics
      3. 8.3.3 Regulatory Information
      4. 8.3.4 Life Expectancy vs Working Voltage
      5. 8.3.5 Safety Limiting Values
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematic
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Maximum Supply Current Equations
          1. 9.2.2.1.1 ISO7420
          2. 9.2.2.1.2 ISO7421
        2. 9.2.2.2 Typical Supply Current Equations:
          1. 9.2.2.2.1 ISO7420
          2. 9.2.2.2.2 ISO7421
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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メカニカル・データ（パッケージ｜ピン）
  • D|8
サーマルパッド・メカニカル・データ
発注情報

8 Detailed Description

8.1 Overview

The isolator in Figure 19 is based on a capacitive isolation barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to
150 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a single- ended input signal entering the HF-channel is split into a differential signal via the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the low-frequency channel.

Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer.

8.2 Functional Block Diagram

ISO7420E ISO7420FE ISO7421E ISO7421FE fbdc_sllse45.gifFigure 19. Conceptual Block Diagram of a Digital Capacitive Isolator

8.3 Feature Description

ISO742x are available in multiple channel configurations and default output state options to enable wide variety of application uses.

PRODUCT DATA RATE DEFAULT OUTPUT RATED TA CHANNEL DIRECTION
ISO7420E 50 Mbps High –40°C to 125°C Same
ISO7420FE Low
ISO7421E High Opposite
ISO7421FE Low

8.3.1 Insulation and Safety-Related Specifications for D-8 Package

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
L(I01) Minimum air gap (clearance) Shortest terminal-to-terminal distance through air 4 mm
L(I02) Minimum external tracking (creepage) Shortest terminal-to-terminal distance across the package surface 4 mm
CTI Tracking resistance (comparative tracking index) DIN EN 60112 (VDE 0303-11); IEC 60112 >400 V
Minimum internal gap (internal clearance) Distance through the insulation 0.014 mm
RIO Isolation resistance, input to output(1) VIO = 500 V, TA = 25°C >1012 Ω
VIO = 500 V, 100°C ≤ TA ≤ max >1011 Ω
CIO Barrier capacitance, input to output(1) VIO = 0.4 sin (2πft), f = 1 MHz 1 pF
CI Input capacitance(2) VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V 1 pF
(1) All pins on each side of the barrier tied together creating a two-terminal device.
(2) Measured from input pin to ground.

NOTE

Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.

Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.

8.3.2 Insulation Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER(1) TEST CONDITIONS SPECIFICATION UNIT
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM Maximum workingisolation voltage 566 VPEAK
VPR Input-to-output test voltage Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial Discharge < 5 pC		 906 VPEAK
Method b1,
VPR = VIORM x 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC		 1062
After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC		 680
VIOTM Maximum transient isolation voltage VTEST = VIOTM = 4242 VPK
t = 60 sec (qualification)
t= 1 sec (100% production)		 4242 VPEAK
RS Isolation resistance VIO = 500 V at TS = 150°C >109 Ω
Pollution degree 2
UL 1577
VISO Maximum withstand isolation voltage VTEST = VISO = 2500 VRMS, t = 60 sec (qualification);
VTEST = 1.2 x VISO = 3000 VRMS, t = 1 sec (100% production)		 2500 VRMS
(1) Climatic Classification 40/125/21

Table 1. IEC 60664-1 Ratings Table

PARAMETER TEST CONDITIONS SPECIFICATION
Basic isolation group Material group II
Installation classification Rated mains voltage ≤ 150 VRMS I–IV
Rated mains voltage ≤ 300 VRMS I–III

8.3.3 Regulatory Information

VDE CSA UL CQC
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 61010-1 (VDE 0411-1):2011-07 Approved under CSA Component Acceptance Notice 5A, IEC 60950-1, and IEC 61010-1 Recognized under UL 1577 Component Recognition Program Certified according to GB 4943.1-2011
Basic Insulation;
Maximum Transient Isolation Voltage, 4242 VPK;
Maximum Working Isolation Voltage, 566 VPK		 2500 VRMS Isolation Rating;
Basic insulation per CSA 60950-1-07+A1 and IEC 60950-1 2nd Ed+A1, 384 VRMS maximum working voltage;
CSA 61010-1-04 and IEC 61010-1 2nd Ed, 300 VRMS maximum working voltage for basic insulation and 150 VRMS for reinforced insulation		 Single Protection Isolation Voltage, 2500 VRMS(1) Basic Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS maximum working voltage
Certificate number: 40016131 Master contract number: 220991 File number: E181974 Certificate number: CQC14001109540
(1) Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.

8.3.4 Life Expectancy vs Working Voltage

ISO7420E ISO7420FE ISO7421E ISO7421FE g001_llse45.gifFigure 20. Life Expectancy vs Working Voltage

8.3.5 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IS Safety input, output, or supply current θJA = 212°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C 107 mA
θJA = 212°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C 164
TS Maximum safety temperature 150 °C

The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed in the JESD51-3, Low-Effective-Thermal-Conductivity Test Board for Leaded Surface-Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

ISO7420E ISO7420FE ISO7421E ISO7421FE thremal_curve_llse45.gifFigure 21. θJC Thermal Derating Curve per VDE

8.4 Device Functional Modes

Table 2. Functional Table(1)

VCCI VCCO INPUT
INA, INB		 OUTPUT
OUTA, OUTB
ISO7420E / ISO7421E ISO7420FE / ISO7421FE
PU PU H H H
L L L
Open H(2) L(3)
PD PU X H(2) L(3)
X PD X Undetermined Undetermined
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.1 V); X = Irrelevant; H = High level; L = Low level;
(2) In fail-safe condition, output defaults to high level
(3) In fail-safe condition, output defaults to low level

8.4.1 Device I/O Schematic

ISO7420E ISO7420FE ISO7421E ISO7421FE device_schematic.gifFigure 22. Device I/O Schematics