JAJSCV2F November   2016  – October 2024 ISO7730-Q1 , ISO7731-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics—5-V Supply
    10. 5.10 Supply Current Characteristics—5-V Supply
    11. 5.11 Electrical Characteristics—3.3-V Supply
    12. 5.12 Supply Current Characteristics—3.3-V Supply
    13. 5.13 Electrical Characteristics—2.5-V Supply 
    14. 5.14 Supply Current Characteristics—2.5-V Supply
    15. 5.15 Switching Characteristics—5-V Supply
    16. 5.16 Switching Characteristics—3.3-V Supply
    17. 5.17 Switching Characteristics—2.5-V Supply
    18. 5.18 Insulation Characteristics Curves
    19. 5.19 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Electromagnetic Compatibility (EMC) Considerations
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device I/O Schematics
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Insulation Lifetime
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 PCB Material
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Related Links
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DBQ|16
  • DW|16
サーマルパッド・メカニカル・データ
発注情報

5.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
DW-16 DBQ-16
CLR External clearance(1) Shortest terminal-to-terminal distance through air >8 >3.7 mm
CPG External creepage(1) Shortest terminal-to-terminal distance across the package surface >8 >3.7 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >17  >17   μm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112, UL 746A >600 >600 V
Material group According to IEC 60664-1 I I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 150 VRMS I-IV I-IV
Rated mains voltage ≤ 300 VRMS I-IV I-III
Rated mains voltage ≤ 600 VRMS I-IV n/a
Rated mains voltage ≤ 1000 VRMS I-III n/a
DIN EN IEC 60747-17 (VDE 0884-17)(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) ISO773x 2121 566 VPK
VIOWM Maximum working isolation voltage AC voltage; Time dependent dielectric breakdown (TDDB) Test; SeeSection 8.2.3.1 ISO773x 1500 400 VRMS
VIOWM Maximum working isolation voltage DC voltage ISO773x 2121 566 VDC
VIOTM  Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification);
VTEST = 1.2 x VIOTM, t= 1 s (100% production) 		 8000 4242 VPK
VIMP Maximum impulse voltage(3) Tested in air, 1.2/50-μs waveform per IEC 62368-1 ISO773x 8000 5000 VPK
VIOSM Maximum surge isolation voltage(4) VIOSM  ≥ 1.3 x VIMP; Tested in oil (qualification test),
1.2/50-μs waveform per IEC 62368-1		 ISO773x 12800 10000 VPK
qpd Apparent charge(5) Method a, After Input/Output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 x VIORM, tm = 10 s		 ≤5 ≤5 pC
qpd Apparent charge(5) Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;		 Vpd(m) = 1.6 x VIORM, tm = 10 s (ISO773x) ≤5 ≤5 pC
qpd Apparent charge(5) Method b; At routine test (100% production) and preconditioning (type test);
Vini = 1.2 x VIOTM, tini = 1 s;
Vpd(m) = 1.875 x VIORM (ISO773x) , tm = 1 s (method b1) or
Vpd(m) = Vini, tm = tini (method b2)		 ≤5 ≤5 pC
CIO Barrier capacitance, input to output(6) VIO = 0.4 x sin (2πft), f = 1 MHz ≅0.7 ≅0.7 pF
RIO Isolation resistance(6) VIO = 500 V, TA = 25°C >1012 >1012 Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C >1011 >1011
VIO = 500 V at TS = 150°C >109 >109
Pollution degree 2 2
Climatic category 55/125/21 55/125/21
UL 1577
VISO Maximum withstanding isolation voltage VTEST = VISO , t = 60 s (qualification),
VTEST = 1.2 x VISO, t = 1 s (100% production)		 5000 3000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed-circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation  only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package
(4) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier tied together creating a two-terminal device.