A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 8-15). Layer stacking must be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer.

• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of the inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100pF/inch².
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.
• A low-ESR ceramic bypass-capacitor should be connected between the V_CC and GND pins for both the supply. The recommended capacitor value can range from 0.1μF to 10μF. The capacitor must have a voltage rating of 10V minimum and a X5R or X7R dielectric. The optimum placement of decap is closest to the V_CC and GND pins.
• The connections between the device D1 and D2 pins and the transformer primary endings, and the connection of the device V_CC1 pin and the transformer center-tap must be as close as possible for minimum trace inductance. And 10μF capacitor should be connected close to the transformer center-tap pin. Length matching of D1 and D2 traces will provide best performance in efficiency and EMI.
• The rectifier diodes should be Schottky diodes with low forward voltage in the 10mA to 100mA current range to maximize efficiency.

If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep the planes symmetrical. This design makes the stack mechanically stable and prevents warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.

For detailed layout recommendations, refer to the Digital Isolator Design Guide.