SLLSEP1B July   2015  – June 2016 ISO7810

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Rating
    6. 6.6  Insulation Characteristics
    7. 6.7  Regulatory Information
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics—5-V Supply
    10. 6.10 Supply Current Characteristics—5-V Supply
    11. 6.11 Electrical Characteristics—3.3-V Supply
    12. 6.12 Supply Current Characteristics—3.3-V Supply
    13. 6.13 Electrical Characteristics—2.5-V Supply
    14. 6.14 Supply Current Characteristics—2.5-V Supply
    15. 6.15 Switching Characteristics—5-V Supply
    16. 6.16 Switching Characteristics—3.3-V Supply
    17. 6.17 Switching Characteristics—2.5-V Supply
    18. 6.18 Insulation Characteristics Curves
    19. 6.19 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Electromagnetic Compatibility (EMC) Considerations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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発注情報

8 Detailed Description

8.1 Overview

The ISO7810x device has an ON-OFF Keying (OOK) modulation scheme to transmit the digital data across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. These devices also incorporates advanced circuit techniques to maximize the CMTI performance and minimize the radiated emissions due the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 17, shows a functional block diagram of a typical channel.

8.2 Functional Block Diagram

ISO7810 ISO7810F fbd_sllsej0.gif Figure 17. Conceptual Block Diagram of a Digital Capacitive Isolator

Figure 18 shows how the ON/OFF keying scheme works.

ISO7810 ISO7810F on_off_keying_sllsem2.gif Figure 18. On-Off Keying (OOK) Based Modulation Scheme

8.3 Feature Description

The ISO7810 is available in both default output state options to enable a variety of application uses. Table 1 provides an overview of the device features.

Table 1. Device Features

PART NUMBER RATED ISOLATION MAXIMUM DATA RATE DEFAULT OUTPUT
ISO7810 5700 VRMS / 8000 VPK (1) 100 Mbps High
ISO7810F 5700 VRMS / 8000 VPK (1) 100 Mbps Low
(1) See the Regulatory Information section for detailed isolation ratings.

8.3.1 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level performance and reliability depends, to a large extent, on the application board design and layout, the ISO7810x device incorporates many chip-level design improvements for overall system robustness. Some of these improvements include:

  • Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
  • Low-resistance connectivity of ESD cells to supply and ground pins.
  • Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
  • Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path.
  • PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic SCRs.
  • Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

8.4 Device Functional Modes

Table 2 lists the ISO7810x functional modes.

Table 2. Function Table(1)

VCC1 VCC2 INPUT
(IN)(3)		 OUTPUT
(OUT)		 COMMENTS
PU PU H H Normal Operation:
A channel output assumes the logic state of the input.
L L
Open Default Default mode: When IN is open, the corresponding channel output goes to the default logic state. Default = High for ISO7810 and Low for ISO7810F.
PD PU X Default Default mode: When VCC1 is unpowered, a channel output assumes the logic state based on the selected default option. Default = High for ISO7810 and Low for ISO7810F.
When VCC1 transitions from unpowered to powered-up, a channel output assumes the logic state of the input.
When VCC1 transitions from powered-up to unpowered, channel output assumes the selected default state.
X PD X Undetermined When VCC2 is unpowered, a channel output is undetermined (2).
When VCC2 transitions from unpowered to powered-up, a channel output assumes the logic state of its input
(1) PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H = High level; L = Low level
(2) The outputs are in undetermined state when 1.7 V < VCC1, VCC2 < 2.25 V.
(3) A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.

8.4.1 Device I/O Schematics

ISO7810 ISO7810F device_IO_schematic_sllsep1.gif Figure 19. Device I/O Schematics