SLLSEP1B July 2015 – June 2016 ISO7810
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Power Rating
- 6.6 Insulation Characteristics
- 6.7 Regulatory Information
- 6.8 Safety Limiting Values
- 6.9 Electrical Characteristics—5-V Supply
- 6.10 Supply Current Characteristics—5-V Supply
- 6.11 Electrical Characteristics—3.3-V Supply
- 6.12 Supply Current Characteristics—3.3-V Supply
- 6.13 Electrical Characteristics—2.5-V Supply
- 6.14 Supply Current Characteristics—2.5-V Supply
- 6.15 Switching Characteristics—5-V Supply
- 6.16 Switching Characteristics—3.3-V Supply
- 6.17 Switching Characteristics—2.5-V Supply
- 6.18 Insulation Characteristics Curves
- 6.19 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Applications and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ（パッケージ｜ピン）
- DWW|16
- DW|16
サーマルパッド・メカニカル・データ
- DW|16
発注情報
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 23). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer.
- Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link.
- Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow.
- Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/in2.
- Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.
For detailed layout recommendations, see the application note, Digital Isolator Design Guide (SLLA284).
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
Figure 23. Layout Example