SLLSEP1B
July 2015 – June 2016
ISO7810
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Power Rating
6.6
Insulation Characteristics
6.7
Regulatory Information
6.8
Safety Limiting Values
6.9
Electrical Characteristics—5-V Supply
6.10
Supply Current Characteristics—5-V Supply
6.11
Electrical Characteristics—3.3-V Supply
6.12
Supply Current Characteristics—3.3-V Supply
6.13
Electrical Characteristics—2.5-V Supply
6.14
Supply Current Characteristics—2.5-V Supply
6.15
Switching Characteristics—5-V Supply
6.16
Switching Characteristics—3.3-V Supply
6.17
Switching Characteristics—2.5-V Supply
6.18
Insulation Characteristics Curves
6.19
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Electromagnetic Compatibility (EMC) Considerations
8.4
Device Functional Modes
8.4.1
Device I/O Schematics
9
Applications and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curve
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.1.1
PCB Material
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Related Links
12.3
Receiving Notification of Documentation Updates
12.4
Community Resources
12.5
Trademarks
12.6
Electrostatic Discharge Caution
12.7
Glossary
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
DWW|16
DW|16
サーマルパッド・メカニカル・データ
DW|16
QFND505A
発注情報
sllsep1b_oa
sllsep1b_pm
5 Pin Configuration and Functions
DW Package
16-Pin SOIC
Top View
DWW Package
16-Pin SOIC
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
DW
DWW
EN2
—
13
I
Output enable 2. Output pin on side 2 is enabled when EN2 is high or open and in high-impedance state when EN2 is low.
GND1
1, 7
2, 8
—
Ground connection for V
CC1
GND2
9, 16
9, 15
—
Ground connection for V
CC2
IN
4
5
I
Input channel
NC
2, 5, 6, 8, 10, 11, 12, 15
3, 4, 6, 7, 10, 11, 14
—
Not connected
OUT
13
12
O
Output channel
V
CC1
3
1
—
Power supply, side 1
V
CC2
14
16
—
Power supply, side 2