JAJSCT7A March   2016  – August 2016 ISO7820LL , ISO7821LL

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  DC Electrical Characteristics
    10. 6.10 DC Supply Current Characteristics
    11. 6.11 Switching Characteristics
    12. 6.12 Insulation Characteristics Curves
    13. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Detailed Description

8.1 Overview

The ISO782xLL is a family of isolated LVDS buffers. The differential signal received on the LVDS input pins is first converted to CMOS logic levels. The signal is then transmitted across a silicon-dioxide (SiO2) based capacitive-isolation barrier using an on-off keying (OOK) modulation scheme. A high frequency carrier transmitted across the barrier represents one logic state and an absence of a carrier represents the other logic state. On the other side of the barrier a demodulator converts the OOK signal back to logic levels, which is then converted to LVDS outputs by a differential driver. These devices incorporate advanced circuit techniques to maximize CMTI performance and minimize radiated emissions.

The ISO782xLL family of devices is TIA/EIA-644-A standard compliant. The LVDS transmitters drive a minimum differential-output voltage magnitude of 250 mV into a 100-Ω load, and the LVDS receivers are capable of detecting differential signals ≥50 mV in magnitude. The device consumes 10 mA per channel at 100 Mbps with 5-V supplies.

The Functional Block Diagram section shows a conceptual block diagram of one channel of the ISO782xLL family of devices.

8.2 Functional Block Diagram

ISO7820LL ISO7821LL fbd_sllset8.gif

8.3 Feature Description

The ISO782xLL family of devices is available in two channel configurations with a default differential high-output state.

PART NUMBER CHANNEL DIRECTION RATED ISOLATION MAXIMUM DATA RATE DEFAULT DIFFERENTIAL OUTPUT
ISO7820LL 2 Forward 5700 VRMS / 8000 VPK (1) 100 Mbps High
ISO7821LL 1 Forward, 1 Reverse
(1) See the Safety-Related Certifications section for detailed isolation ratings.

8.4 Device Functional Modes

Table 1 lists the functional modes for the ISO782xLL family of devices.

Table 1. ISO782xLL Function Table(1)

VCCI VCCO INPUT
(INx±)(2)		 OUTPUT ENABLE
(ENx) 		OUTPUT
(OUTx±)(3)		 COMMENTS
PU PU H H or open H Normal Operation:
A channel output assumes the logic state of the input.
L H or open L
I H or open H or L
X PU X L Z A low-logic state at the output enable causes the outputs to be in high impedance.
PD PU X H or open H Default mode: When VCCI is unpowered, a channel output assumes the logic high state.
When VCCI transitions from unpowered to powered up, a channel output assumes the logic state of the input.
When VCCI transitions from powered up to unpowered, a channel output assumes the selected default high state.
X PD X X Undetermined When VCCO is unpowered, a channel output is undetermined.
When VCCO transitions from unpowered to powered-up, a channel output assumes the logic state of the input
(1) VCCI = input-side VCC; VCCO = output-side VCC; PU = powered up (VCCx ≥ 2.25 V); PD = powered down (VCCx ≤ 1.7 V); X = irrelevant
(2) Input (INx±): H = high level (VID ≥ 50 mV); L = low level (VID ≤ –50 mV); I = indeterminate (–50 mV < VID < 50 mV)
(3) Output (OUTx±): H = high level (VOD ≥ 250 mV); L = low level (VOD ≤ –250 mV); Z = high impedance.

8.4.1 Device I/O Schematics

ISO7820LL ISO7821LL device_IO_sllset8.gif Figure 28. Device I/O Schematics