JAJSCT7A March   2016  – August 2016 ISO7820LL , ISO7821LL

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  DC Electrical Characteristics
    10. 6.10 DC Supply Current Characteristics
    11. 6.11 Switching Characteristics
    12. 6.12 Insulation Characteristics Curves
    13. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

ISO7820LL DW and DWW Packages
16-Pin SOIC
Top View
ISO7820LL ISO7821LL po_iso7820ll_sllset8.gif
ISO7821LL DW and DWW Packages
16-Pin SOIC
Top View
ISO7820LL ISO7821LL po_iso7821llx_sllset5.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
ISO7820LL ISO7821LL
EN1 — 7 I Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in high impedance state when EN1 is low.
EN2 10 10 I Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in high impedance state when EN2 is low.
GND1 2 2 — Ground connection for VCC1
8 8
GND2 9 9 — Ground connection for VCC2
15 15
INA+ 3 3 I Positive differential input, channel A
INA– 4 4 I Negative differential input, channel A
INB+ 6 11 I Positive differential input, channel B
INB– 5 12 I Negative differential input, channel B
NC 7 — — Not connected
OUTA+ 14 14 O Positive differential output, channel A
OUTA– 13 13 O Negative differential output, channel A
OUTB+ 11 6 O Positive differential output, channel B
OUTB– 12 5 O Negative differential output, channel B
VCC1 1 1 — Power supply, side 1, VCC1
VCC2 16 16 — Power supply, side 2, VCC2