JAJSU48A April   2024  – May 2024 ISOM8610

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
  7. 6 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Sizing RIN
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
4-DFG
IEC 60664-1
CLR External clearance(1) Side 1 to side 2 distance through air > 5 mm
CPG External creepage(1) Side 1 to side 2 distance across package surface > 5 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >17 µm
CTI Comparative tracking index IEC 60112; UL 746A >400 V
Material Group According to IEC 60664-1 II
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 150VRMS I-IV
Rated mains voltage ≤ 300VRMS I-IV
Rated mains voltage ≤ 600VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17) (2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 707 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test 500 VRMS
DC voltage 707 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60s (qualification); VTEST = 1.2 × VIOTM, t = 1s (100% production) 5303 VPK
VIMP Maximum impulse voltage(3) Tested in air, 1.2/50µs waveform per IEC 62368-1 7200 VPK
VIOSM Maximum surge isolation voltage(3) Test method per IEC 62368-1, 1.2/50µs waveform,
VTEST = 1.6 × VIMP  or min 10 kVPK (qualification)		 6250 VPK
qpd Apparent charge(4) Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60s; Vpd(m) = 1.2 × VIORM, tm = 10s ≤ 5 pC
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60s;
Vpd(m) = 1.6 × VIORM, tm = 10s		 ≤ 5
Method b: At routine test (100% production), Vini = 1.2 × VIOTM, tini = 1s;
Vpd(m) = 1.875 × VIORM, tm = 1s (method b1) or
Vpd(m) = Vini, tm = tini (method b3)		 ≤ 5
CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2 πft), f = 1MHz 1 pF
RIO Insulation resistance, input to output(5) VIO = 500V,  TA = 25°C > 1012 Ω
VIO = 500V,  100°C ≤ TA ≤ 125°C > 1011
VIO = 500V at  TS = 150°C > 109
Pollution degree 2
Climatic category 55/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO, t = 60s (qualification); VTEST = 1.2 × VISO , t = 1s (100% production) 3750 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) Testing is carried out in air to determine the surge immunity of the package.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.