JAJSE44B May   2017  – April 2018 IWR1642

PRODUCTION DATA.  

  1. 1 デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2 改訂履歴
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
      1. Table 4-3 PAD IO Register Bit Descriptions
    3. 4.3 Signal Descriptions
      1. Table 4-4 Signal Descriptions - Digital
      2. Table 4-5 Signal Descriptions - Analog
    4. 4.4 Pin Multiplexing
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Supply Specifications
    6. 5.6  Power Consumption Summary
    7. 5.7  RF Specification
    8. 5.8  CPU Specifications
    9. 5.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 5.10 Timing and Switching Characteristics
      1. 5.10.1  Power Supply Sequencing and Reset Timing
      2. 5.10.2  Input Clocks and Oscillators
        1. 5.10.2.1 Clock Specifications
      3. 5.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 5.10.3.1 Peripheral Description
        2. 5.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. Table 5-7  SPI Timing Conditions
          2. Table 5-8  SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. Table 5-9  SPI Master Mode Input Timing Requirements (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          4. Table 5-10 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          5. Table 5-11 SPI Master Mode Input Requirements (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 5.10.3.3 SPI Slave Mode I/O Timings
          1. Table 5-12 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          2. Table 5-13 SPI Slave Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        4. 5.10.3.4 Typical Interface Protocol Diagram (Slave Mode)
      4. 5.10.4  LVDS Interface Configuration
        1. 5.10.4.1 LVDS Interface Timings
      5. 5.10.5  General-Purpose Input/Output
        1. Table 5-15 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 5.10.6  Controller Area Network Interface (DCAN)
        1. Table 5-16 Dynamic Characteristics for the DCANx TX and RX Pins
      7. 5.10.7  Serial Communication Interface (SCI)
        1. Table 5-17 SCI Timing Requirements
      8. 5.10.8  Inter-Integrated Circuit Interface (I2C)
        1. Table 5-18 I2C Timing Requirements
      9. 5.10.9  Quad Serial Peripheral Interface (QSPI)
        1. Table 5-19 QSPI Timing Conditions
        2. Table 5-20 Timing Requirements for QSPI Input (Read) Timings
        3. Table 5-21 QSPI Switching Characteristics
      10. 5.10.10 ETM Trace Interface
        1. Table 5-22 ETMTRACE Timing Conditions
        2. Table 5-23 ETM TRACE Switching Characteristics
      11. 5.10.11 Data Modification Module (DMM)
        1. Table 5-24 DMM Timing Requirements
      12. 5.10.12 JTAG Interface
        1. Table 5-25 JTAG Timing Conditions
        2. Table 5-26 Timing Requirements for IEEE 1149.1 JTAG
        3. Table 5-27 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Subsystems
      1. 6.3.1 RF and Analog Subsystem
        1. 6.3.1.1 Clock Subsystem
        2. 6.3.1.2 Transmit Subsystem
        3. 6.3.1.3 Receive Subsystem
      2. 6.3.2 Processor Subsystem
      3. 6.3.3 Host Interface
      4. 6.3.4 Master Subsystem Cortex-R4F Memory Map
      5. 6.3.5 DSP Subsystem Memory Map
    4. 6.4 Other Subsystems
      1. 6.4.1 ADC Channels (Service) for User Application
        1. Table 6-3 GP-ADC Parameter
  7. 7 Monitoring and Diagnostics
    1. 7.1 Monitoring and Diagnostic Mechanisms
      1. 7.1.1 Error Signaling Module
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Application Information
    2. 8.2 Reference Schematic
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
      3. 8.3.3 Stackup Details
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Community Resources
    5. 9.5 商標
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 Export Control Notice
    8. 9.8 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.4 Master Subsystem Cortex-R4F Memory Map

Table 6-1 shows the master subsystem, Cortex-R4F memory map.

NOTE

There are separate Cortex-R4F addresses and DMA MSS addresses for the master subsystem. See the Technical Reference Manual for a complete list.

Table 6-1 Master Subsystem, Cortex-R4F Memory Map

NAME FRAME ADDRESS (HEX) SIZE DESCRIPTION
START END
CPU Tightly-Coupled Memories
TCMA ROM 0x0000_0000 0x0001_FFFF 128 KiB Program ROM
TCM RAM-A 0x0020_0000 0x0023_FFFF (or 0x0027_FFFF) 512 KiB 256/512KB based on variant
TCM RAM-B 0x0800_0000 0x0802_FFFF 192 KB Data RAM
S/W Scratch Pad Memory
SW_ Buffer 0x0C20_0000 0x0C20_1FFF 8 KB S/W Scratchpad memory
System Peripherals
Mail Box
MSS<->RADARSS		 0xF060_1000 0xF060_17FF 2 KB RADARSS to MSS mailbox memory space
0xF060_2000 0xF060_27FF MSS to RADARSS mailbox memory space
0xF060_8000 0xF060_80FF 188 B MSS to RADARSS mailbox Configuration registers
0xF060_8060 0xF060_86FF RADARSS to MSS mailbox Configuration registers
Mail Box
MSS<->DSPSS		 0xF060_4000 0xF060_47FF 2 KB DSPSS to MSS mailbox memory space
0xF060_5000 0xF060_57FF MSS to DSPSS mailbox memory space
0xF060_8400 0xF060_84FF 188 B MSS to DSPSS mailbox Configuration registers
0xF060_8300 0xF060_83FF DSPSS to MSS mailbox Configuration registers
Mail Box
RADARSS<->DSPSS		 0xF060_6000 0xF060_67FF 2 KB RADARSS to DSPSS mailbox memory space
0xF060_7000 0xF060_7FFF DSPSS to RADARSS mailbox memory space
0xF060_8200 0xF060_82FF 188 B RADARSS to DSPSS mailbox Configuration registers
0xF060_8100 0xF060_81FF DSPSS to RADARSS mailbox Configuration registers
PRCM and Control Module 0xFFFF_E100 0xFFFF_E2FF 756 B TOP Level Reset, Clock management registers
0xFFFF_FF00 0xFFFF_FFFF 256 B MSS Reset, Clock management registers
0xFFFF_EA00 0xFFFF_EBFF 512 KB IO Mux module registers
0xFFFF_F800 0xFFFF_FBFF 352 B General-purpose control registers
GIO 0xFFF7_BC00 0xFFF7_BDFF 180 B GIO module configuration registers
DMA-1 0xFFFF_F000 0xFFFF_F3FF 1 KB DMA-1 module configuration registers
DMA-2 0xFCFF_F800 0xFCFF_FBFF 1 KB DMA-2 module configuration registers
DMM-1 0xFCFF_F700 0xFCFF_F7FF 472 B DMM-1 module configuration registers
DMM-2 0xFCFF_F600 0xFCFF_F6FF 472 B DMM-2 module configuration registers
VIM 0xFFFF_FD00 0xFFFF_FEFF 512 B VIM module configuration registers
RTI-A/WD 0xFFFF_FC00 0xFFFF_FCFF 192 B RTI-A module configuration registers
RTI-B 0xFFFF_EE00 0xFFFF_EEFF 192 B RTI-B module configuration registers
Serial Interfaces and Connectivity
QSPI 0xC000_0000 0xC07F_FFFF 8 MB QSPI –flash memory space
0xC080_0000 0xC0FF_FFFF 116 B QSPI module configuration registers
MIBSPI-A 0xFFF7_F400 0xFFF7_F5FF 512 B MIBSPI-A module configuration registers
MIBSPI-B 0xFFF7_F600 0xFFF7_F7FF 512 B MIBSPI-B module configuration registers
SCI-A 0xFFF7_E500 0xFFF7_E5FF 148 B SCI-A module configuration registers
SCI-B 0xFFF7_E700 0xFFF7_E7FF 148 B SCI-B module configuration registers
CAN 0xFFF7_DC00 0xFFF7_DDFF 512 B CAN module configuration registers
RESERVED 0xFFF7_C800 0xFFF7_CFFF 768 B Reserved
0xFFF7_A000 0xFFF7_A1FF 452 B Reserved
I2C 0xFFF7_D400 0xFFF7_D4FF 112 B I2C module configuration registers
Interconnects
PCR-1 0xFFF7_8000 0xFFF7_87FF 1 KiB PCR-1 interconnect configuration port
PCR-2 0xFCFF_1000 0xFCFF_17FF 1 KiB PCR-2 interconnect configuration port
Safety Modules
CRC 0xFE00_0000 0xFEFF_FFFF 16 KiB CRC module configuration registers
PBIST 0xFFFF_E400 0xFFFF_E5FF 464 B PBIST module configuration registers
STC 0xFFFF_E600 0xFFFF_E7FF 284 B STC module configuration registers
DCC-A 0xFFFF_EC00 0xFFFF_ECFF 44 B DCC-A module configuration registers
DCC-B 0xFFFF_F400 0xFFFF_F4FF 44 B DCC-B module configuration registers
ESM 0xFFFF_F500 0xFFFF_F5FF 156 B ESM module configuration registers
CCMR4 0xFFFF_F600 0xFFFF_F6FF 136 B CCMR4 module configuration registers
Other Subsystems
DSS_TPTC0 0x5000 0000 0x5000 0317 792 B TPTC0 module configuration space
DSS_REG 0x5000 0400 0x5000 075F 864 B DSPSS control module registers
DSS_TPTC1 0x5000 0800 0x5000 0B17 792 B TPTC1 module configuration space
DSS_REG2 0x5000 0C00 0x5000 0EA3 676 B DSPSS control module registers
DSS_TPCC0 0x5001 0000 0x5001 3FFF 16 KB TPCC0 module configuration space
DSS_RTIA/WDT 0x5002 0000 0x5002 00BF 192 B DSS_RTIA/WDT configuration space
DSS_SCI 0x5003 0000 0x5003 0093 148 B SCI memory space
DSS_STC 0x5004 0000 0x5004 011B 284 B STC module configuration space
DSS_CBUFF 0x5007 0000 0x5007 0233 564 B Common Buffer module configuration registers
DSS_TPTC2 0x5009 0000 0x5009 0317 792 B TPTC2 module configuration space
DSS_TPTC3 0x5009 0400 0x5009 0717 792 B TPTC3 module configuration space
DSS_TPCC1 0x500A 0000 0x500A 3FFF 16 KB TPCC1 module configuration space
DSS_ESM 0x500D 0000 0x500D 005B 92 B ESM module configuration registers
DSS_RTIB 0x500F 0000 0x500F 00BF 192 B RTI-B module configuration registers
DSS_L3RAM Shared memory 0x5100 0000 0x511F FFFF 2 MB(1) L3 shared memory space
DSS_ADCBUF Buffer 0x5200 0000 0x5200 7FFF 32 KB ADC buffer memory space
DSS_CBUFF_FIFO 0x5202 0000 0x5202 3FFF 16 KB Common buffer FIFO space
DSS_HSRAM1 0x5208 0000 0x5208 7FFF 32 KB Handshake memory space
DSS_DSP_L2_UMAP1 0x577E 0000 0x577F FFFF 128 KB L2 RAM space
DSS_DSP_L2_UMAP0 0x5780 0000 0x5781 FFFF 128 KB L2 RAM space
DSS_DSP_L1P 0x57E0 0000 0x57E0 7FFF 32 KB L1 program memory space
DSS_DSP_L1D 0x57F0 0000 0x57F0 7FFF 32 KB L1 data memory space
Peripheral Memories (System and Nonsystem)
CAN RAM 0xFF1E_0000 0xFF1F_FFFF 128 KB CAN RAM memory space
RESERVED 0xFF50_0000 0xFF51_FFFF 68 KB Reserved
DMA1 RAM 0xFFF8_0000 0xFFF8_0FFF 4 KB DMA1 RAM memory space
DMA2 RAM 0xFCF8 1000 0xFCF8_0FFF 4 KB DMA2 RAM memory space
VIM RAM 0xFFF8_2000 0xFFF8_2FFF 2 KB VIM RAM memory space
MIBSPIB-TX RAM 0xFF0C_0000 0xFF0C_01FF 0.5 KB MIBSPIB-TX RAM memory space
MIBSPIB-RX RAM 0xFF0C_0200 0xFF0C_03FF 0.5 KB MIBSPIB-RX RAM memory space
MIBSPIA-TX RAM 0xFF0E_0000 0xFF0E_01FF 0.5 KB MIBSPIA-TX RAM memory space
MIBSPIA- RX RAM 0xFF0E_0200 0xFF0E_03FF 0.5 KB MIBSPIA- RX RAM memory space
Debug Modules
Debug subsystem 0xFFA0_0000 0xFFAF_FFFF 244 KB Debug subsystem memory space and registers
(1) 768 KB memory within 2 MB memory space