JAJSHY4A September 2019 – January 2022 IWR1843
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
INTERFACE | SIGNAL NAME | PIN TYPE | DESCRIPTION | BALL NO. |
---|---|---|---|---|
Transmitters | TX1 | O | Single ended transmitter1 o/p | B4 |
TX2 | O | Single ended transmitter2 o/p | B6 | |
TX3 | O | Single ended transmitter3 o/p | B8 | |
Receivers | RX1 | I | Single ended receiver1 i/p | M2 |
RX2 | I | Single ended receiver2 i/p | K2 | |
RX3 | I | Single ended receiver3 i/p | H2 | |
RX4 | I | Single ended receiver4 i/p | F2 | |
Reset | NRESET | I | Power on reset for chip. Active low | R3 |
Reference Oscillator | CLKP | I | In XTAL mode: Input for the reference crystal In External clock mode: Single ended input reference clock port | B15 |
CLKM | I | In XTAL mode: : Feedback drive for the reference crystal In External clock mode: Connect this port to ground | C15 | |
Reference clock | OSC_CLKOUT | O | Reference clock output from clocking subsystem after cleanup PLL (1.4V output voltage swing). | A14 |
Bandgap voltage | VBGAP | O | Device's Band Gap Reference Output | B10 |
Power supply | VDDIN | Power | 1.2V digital power supply | H15, N11, P15, R6 |
VIN_SRAM | Power | 1.2V power rail for internal SRAM | G15 | |
VNWA | Power | 1.2V power rail for SRAM array back bias | P14 | |
VIOIN | Power | I/O Supply (3.3V or 1.8V): All CMOS I/Os would operate on this supply | R10, F15 | |
VIOIN_18 | Power | 1.8V supply for CMOS IO | R9 | |
VIN_18CLK | Power | 1.8V supply for clock module | B11 | |
VIOIN_18DIFF | Power | 1.8V supply for LVDS port | D15 | |
VPP | Power | Voltage supply for fuse chain | L13 | |
Power supply | VIN_13RF1 | Power | 1.3V Analog and RF supply,VIN_13RF1 and VIN_13RF2 could be shorted on the board | G5, H5, J5 |
VIN_13RF2 | Power | 1.3V Analog and RF supply | C2,D2 | |
VIN_18BB | Power | 1.8V Analog base band power supply | K5, F5 | |
VIN_18VCO | Power | 1.8V RF VCO supply | B12 | |
VSS | Ground | Digital ground | L5, L6, L8, L10, K7, K8, K9, K10, K11, J6, J7, J8, J10, H7, H9, H11, G6, G7, G8, G10, F9, F11, E5, E6, E8, E10, E11, R15 | |
VSSA | Ground | Analog ground | A1, A3, A5, A7, A15, B1, B3, B5, B7, C1, C3, C4, C5, C6, C7, E1, E2, E3, F3, G1, G2, G3, H3, J1, J2, J3, K3, L1, L2, L3, M3, N1, N2, N3, R1, A13, C8,A9, B9, C9, B14, C14 | |
Internal LDO output/inputs | VOUT_14APLL | O | Internal LDO output | A10 |
VOUT_14SYNTH | O | Internal LDO output | B13 | |
VOUT_PA | IO | When internal PA LDO is used this pin provides the output voltage of the LDO. When the internal PA LDO is bypassed and disabled 1V supply should be fed on this pin. This is mandatory in 3TX simultaneous use case. | A2, B2 | |
Test and Debug output for pre-production phase. Can be pinned out on production hardware for field debug | Analog Test1 / ADC1 | IO | ADC Channel 1(1) | P1 |
Analog Test2 / ADC2 | IO | ADC Channel 2(1) | P2 | |
Analog Test3 / ADC3 | IO | ADC Channel 3(1) | P3 | |
Analog Test4 / ADC4 | IO | ADC Channel 4(1) | R2 | |
ANAMUX / ADC5 | IO | ADC Channel 5(1) | C13 | |
VSENSE / ADC6 | IO | ADC Channel 6(1) | D14 |